$ python sim.py Mode="FB" R1="115k 0.1%" R2="59k 0.1%" Vref="4.096V 0.1%"
R1: 114.885K <= 115.0K <= 115.115K
R2: 58.941K <= 59.0K <= 59.059K
Vref: 4.0919V <= 4.096V <= 4.1001V
Vout: 12.0533V <= 12.07855V <= 12.10379V
Range: +/-0.209%
$ python sim.py Mode="FB" R1="10k 0.1%" R2="10k 0.1%" Vref="4.096V 0.1%"
R1: 9.99K <= 10.0K <= 10.01K
R2: 9.99K <= 10.0K <= 10.01K
Vref: 4.0919V <= 4.096V <= 4.1001V
Vout: 8.17645V <= 8.19119V <= 8.20594V
Range: +/-0.180%
Thread starter | Similar threads | Forum | Replies | Date |
---|---|---|---|---|
A | Digital to analog resistive circuit | Analog & Mixed-Signal Design | 44 | |
M | Resistive loads in DC/DC converters or inverters | Power Electronics | 11 | |
Basic question from one rusty on passives | General Electronics Chat | 6 | ||
H | BJT Resistive Divider Biasing | Homework Help | 13 | |
H | AC Capacitive Voltage Divider Ratio Versus Resistive | Homework Help | 11 |
by Aaron Carman
by Duane Benson
by Jake Hertz
by Jake Hertz