Reset switch of CD4017 counter doesn't work properly on my circuit, why?

danadak

Joined Mar 10, 2018
4,057
If you read the referenced material you will find (1'st ap note) -

upload_2018-7-13_7-17-49.png

And (TI ap note) -

It is not possible to prevent metastability in flip-flops, so systems must be designed so that, to a sufficient degree of probability,
no malfunctions appear in the circuitry.
Your comment -

So a ratty signal to a DC latch set/reset input could theoretically cause a momentary metastable state but it has to eventually go to the commanded state. A latch cannot indefinitely stay in the metastable condition or stay in an illegal state.
Where did you read this ?

The 2'ond ap note also specifically makes clear total elimination is NOT possible.
As do the others in their findings.


Regards, Dana.
 
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AnalogKid

Joined Aug 1, 2013
10,987
I don't see any conflict. Neither of your two quotes address what Wally said - that a metastable condition is, as its name says, not stable. It is a transient condition and always leads to one of two logical states.

ak
 

crutschow

Joined Mar 14, 2008
34,285
Where did you read this ?
No where.
It is just logical thinking.
Do you think a device can stay in the metastable state forever?
The 2'ond ap note also specifically makes clear total elimination is NOT possible.
As do the others in their findings.
I never said it was eliminated.
But a metastable state does not last forever, so it will eventually go to the state as defined by the Set/Reset input.
 

danadak

Joined Mar 10, 2018
4,057
Do you think a device can stay in the metastable state forever?
Yes, as long as there is power available. Of course the sun goes red giant in 10M+ years and melts all silicon, so you are correct, but then what logical state would that be ?

The papers specifically DO NOT STATE that the problem ALWAYS terminates leaving meta instability. Logically I do not like the result either, but the work does not conclude what you would like it to do. Like BER in F-F toggling, once in a blue moon, all conditions being equal, a F-F fails to function correctly. There is a wealth of information in NASA papers on this very problem, how does one recover from failed logic functioning in long term mission requirements.

There are similar studies in Ethernet Physical Layer.

Just as the Heisenberg uncertainty principle guarantees you will NEVER know precisely location and speed simultaneously so goes the research work on this topic. Uncertainty prevails.


Regards, Dana.
 

crutschow

Joined Mar 14, 2008
34,285
so you are correct, but then what logical state would that be ?
In this case it has to be the state that the Set/Reset input is in.
You are still confusing a DC set/reset input with a clocked flip-flop input (which I agree could end up in either state after a metastable condition).
I'll repeat, those paper's are referring to clocked logic, which this is not.
I don't understand why you don't see the difference(?).
 

danadak

Joined Mar 10, 2018
4,057
And I do not understand why you do not see the difference in not meeting datasheet specs, or for that matter the clear results of the papers about metastability or the need to advocate good practices on working with logic for the community.

But then we view the universe differently ?

Yes, its clocked logic that is of concern, do we know how the reset is implemented in the flops internally ? Short answer is NO. In fact almost across the board most logic manufacturers do not spec slow rise time effects in their CMOS parts (some have ap notes on that however), but we know as a community this is a problem to dig into if not speced.

For the life of me I do not understand why anyone would defend feeding logic crappy signals. Whether or not its clocked. The exception of course conditioned logic like a Schmidt input.

Meta-instability exists in this basic non clocked element -



I am sure, reading your posts, you are not one of those who would advocate marginal or out of spec practices.

Regards, Dana.
 

crutschow

Joined Mar 14, 2008
34,285
And I do not understand why you do not see the difference in not meeting datasheet specs
Because those specs are minimum pulse widths to insure that the signal is long enough to perform the set/reset functions and, after the switch bounces have subsided, all those specs are met.
What happens during the bounce period is immaterial.
or for that matter the clear results of the papers about metastability
And, once again I state, those "clear results" are clearly for clocked logic, which this is not.
But then we view the universe differently ?
I don't know about the universe, but we do seem to about metastability in unclocked digital circuits. :rolleyes:
Meta-instability exists in this basic non clocked element -

You really need to think through how the circuit works in this situation, instead of just blindly referencing some papers and insisting that it applies here.

In this latch circuit the S and R inputs are normally low.
That circuit can be in a metastable state only if both the Set and Reset Signals are low during the application of a signal (which could occur during switch bounce).
But once one of those inputs stays high (such as after the bounce period) then that respective NOR has no choice but for its output to go low, driving the other output high.
No metastability is possible, because now only one state is possible for the latch.

So adding extra circuitry to avoid switch bounce to a set/reset input is a completely unnecessary added complexity.
I am sure, reading your posts, you are not one of those who would advocate marginal or out of spec practices.
That's very kind of you, and I don't.
But I'm not pedantic enough to believe that this is one of those situations.

But I believe I've said my last on this subject.
I'm apparently not going to convert you to my viewpoint, and you certainly aren't going to convert me to yours. :rolleyes:
 

Sensacell

Joined Jun 19, 2012
3,432
We are talking about a RESET input driven by a mechanical switch.
If one examines a typical switch bounce event, there are many nasty things happening...
Bouncy_Switch.png
But... there persists a valid logic level for significant periods of time that guaranty that the RESET will be asserted.
All the meta-mayhem in-between has zero impact on the final state.

RESET is not a bi-stable state, once it's reset, you can hammer on the reset input all day long and it's not going to flip back to the previous state.
 

danadak

Joined Mar 10, 2018
4,057
The research community clearly -

1) Support metastability in both non clocked and clocked logic. Thats a fact.
Read the papers. Instructive. I have, blindness is not one of my attributes, yet.

2) We collectively do not know how the reset was implemented in the 4017.
Is it SR based ? Is there an internal feedback path created when the input
spends excess time in the active region.

But I believe I've said my last on this subject.

Regards, Dana.
 
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Thread Starter

nornandxor

Joined Dec 11, 2017
148
If you read you referenced material you will see that metastability occurs in clocked circuits when an input data change to a latch occurs near a clock edge, and the bistable circuit goes into a metastable condition. However, it eventually goes into one of its two stable states..

So a ratty signal to a DC latch set/reset input could theoretically cause a momentary metastable state but it has to eventually go to the commanded state. A latch cannot indefinitely stay in the metastable condition or stay in an illegal state.
You are worrying about an issue that does not apply here.
Are you sure that the reset signal is subject to metastability?
Neither sure nor unsure, did not design the 4017. So best advice is adhere to data
sheet specs and best practices ? Runt and ill formed logic pulses not best practice.

Regards, Dana.
I agree that bouncing on a level-sensitive input is highly unlikely to be the problem.
When the Reset Switch is pressed then the voltage of MR(Pin 15) should be as +Vcc.
And you haven't show how many volts that the Vcc is?
If you read you referenced material you will see that metastability occurs in clocked circuits when an input data change to a latch occurs near a clock edge, and the bistable circuit goes into a metastable condition. However, it eventually goes into one of its two stable states..

So a ratty signal to a DC latch set/reset input could theoretically cause a momentary metastable state but it has to eventually go to the commanded state. A latch cannot indefinitely stay in the metastable condition or stay in an illegal state.
You are worrying about an issue that does not apply here.
Sorry guys to get back to you late, I appreciate all of you guys and thanks a lot for all the responses and suggested solutions!
I think I know what was wrong about my circuit. I just remembered that my output goes to a transistor latch switch circuit!!! So, when I click the reset switch it does resets both CD4017 Decoders but I was dumb enough to forget that I connected my output 6 months ago to that latch switch to keep my output LED ON no matter!
Now, I have to figure out how to reset both decoders and the modified output by ONE CLICK! ;):cool: I'm thinking of using a two ways normally open tactile switch, yet I will have a concern about the synchronization of which triggers first, ON/OFF or RESET! What do you think!?
 

crutschow

Joined Mar 14, 2008
34,285
I'm thinking of using a two ways normally open tactile switch, yet I will have a concern about the synchronization of which triggers first, ON/OFF or RESET! What do you think!?
I think you need to post the circuits you are trying to trigger so we can give you a good answer. ;)
 

Thread Starter

nornandxor

Joined Dec 11, 2017
148
R1 = 4.7K(or 5.1K) for +5Vcc,
R1 = 10K(or 9.1K) for +9Vcc,
R1 = 12K for +12Vcc.

Please measures the Reset Switch to make sure that it is works fine and also check two wires which connected to the Reset Switch.

Please measures the voltage of the pin 15(MR) when the Reset Switch is pressed and before you press it.
Hi Scott,
Is there a specific formula that you used to come up with these R values for the Reset switch? Does it help if I say the more the R value the more efficient is my Reset switch? Does it work like this?
Thanks
 

ScottWang

Joined Aug 23, 2012
7,397
Hi Scott,
Is there a specific formula that you used to come up with these R values for the Reset switch? Does it help if I say the more the R value the more efficient is my Reset switch? Does it work like this?
Thanks
That was designed for the draw current of R1 is around 1 mA, and that is enough for the CMOS logic ic and the most of applications.
 

ScottWang

Joined Aug 23, 2012
7,397
Got it, thanks!
Sometimes when we design the circuit, it is not just let it works, we still need to considering about the power consumption, especially when you use the battery to power the device, and as the R values, if it is too small then the draw current will be a little higher, but it is too high as 100K then it may catch the noise in some cases, so from 1K to 100K that they all can be work, but choose an appropriate value is what we have to concern.
 

Thread Starter

nornandxor

Joined Dec 11, 2017
148
Sometimes when we design the circuit, it is not just let it works, we still need to considering about the power consumption, especially when you use the battery to power the device, and as the R values, if it is too small then the draw current will be a little higher, but it is too high as 100K then it may catch the noise in some cases, so from 1K to 100K that they all can be work, but choose an appropriate value is what we have to concern.
My input voltage for the current design is 2.6 to 3 volts, so I'm using a 7K resistor for now. I just was wondering because I noticed that it does the reset operation for around 60% of the time.
 

ScottWang

Joined Aug 23, 2012
7,397
My input voltage for the current design is 2.6 to 3 volts, so I'm using a 7K resistor for now. I just was wondering because I noticed that it does the reset operation for around 60% of the time.
Do you mean that the input voltage is the Vcc, if yes then you can use R1 = 2.7K or 3K.
 

Thread Starter

nornandxor

Joined Dec 11, 2017
148
Do you mean that the input voltage is the Vcc, if yes then you can use R1 = 2.7K or 3K.
Yes, it is Vcc. I used the the 7K because thats the available R value that I have at this moment! So, you don't recommend going with higher than 3K, or 7K still fine?
 

ScottWang

Joined Aug 23, 2012
7,397
Yes, it is Vcc. I used the the 7K because thats the available R value that I have at this moment! So, you don't recommend going with higher than 3K, or 7K still fine?
It should be fine, sometimes if you don't have the best one then you can choose the second or third.
 
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