Can anyone provide some good reading on how lowering inductance helps to decrease power?

I am reading about interconnects and they say that the reduction in stack height helps to reduce inductance and therefore reduces power. They don't say why though and how. If it is a simple equation explaining this can someone point it out. Thanks.

 

Can you provide more information?

Maybe the link where you are reading from?

Which power are you talking about? The power of what?

 

Well it was a powerpoint I was reading. They were talking about the stack up used by microprocessor manufs. For example, 4-4-4 where the middle 4 is a core and 4 layers on each side. They stated that if you reduce the stack height by eliminating the core for example would reduce the overall inductance of the stack height and then help to reduce wasted power.

What I do not understand is the relationship between reducing inductance and reducing power dissipation?

I don't quite understand enough about the system to explain but I just wanted to understand the concept they were getting at.

Thanks for the help.

 

I think they don't talk about power dissipation which is lost a heat but about power required to charge up this inductance which makes the system respond slower.

 

Is there any reading or incite you can give to help me understand the relationship between reducing parasitics and saving in terms of power efficiency?

EDIT: Hopefully I can try to explain again.

If I have multiple layers of different dielectrics and it has a thick core dielectric with some loss tangent x. If I reduce the total layers by some y percentage, eliminating the thick core dielectric, what are the equations governing that reduction in terms of power savings, efficiency, decreased L & C, etc. This is what I need help in understand.

Thanks in advance.