Read Write RAM in Logisim

I am trying to build a nibble sized read write RAM using only gates and flip flops and I am having a lot of trouble. This is what I have so far and it looks like it works but I am not sure. Please help.

When read/write is 0 and enable is 1 then I show it in the output data and when read is 1 then I show it in the output data as well.

I will eventually have to combine multiple of these to create a 16 nibble ram ...