Hi, I hope all members are doing well.
I would like to ask a couple of of questions regarding look up tables.
1) how can we create 2-1 multiplexer using only 2 input look up tables?
2) can outputs of one set of look up tables be used to map SRAM bits of another look up table?
Any help is much appreciated.

 

Hi, I hope all members are doing well.
I would like to ask a couple of of questions regarding look up tables.
1) how can we create 2-1 multiplexer using only 2 input look up tables?
2) can outputs of one set of look up tables be used to map SRAM bits of another look up table?
Any help is much appreciated.

1. 2-inputs can specify 4 choices. If the data in the table is two bits wide, then each entry can specify that each of the outputs is equal to either input A or input B.
2. Sure. you can have as amny layers as you want.

There were early versions of the FPGA (Xilinx, I think) that had 32x1 bit RAM cells, that could implement any Boolean function of 5 variables. Why did they do this? Because RAM cells are smaller and more regular than anything else you can do on a wafer.

 

Thanks a lot @Papabravo .
with regards to my second question how can we implement a 4 input LUT using only 2 input LUT.

 

Thanks a lot @Papabravo .
with regards to my second question how can we implement a 4 input LUT using only 2 input LUT.

I'm not quite following you. Perhaps a diagram of what you are thinking about might help

 

Sorry for not being clear.
let me rephrase
How can we implement a four variable function using only two input LUT?

 

Welcome to AAC!

1) how can we create 2-1 multiplexer using only 2 input look up tables?

The purpose of look-up tables is to simplify something and/or gain speed. For example a table with transcendental functions like sin, cos, tan. Instead of calculating them every time they occur, using a look-up table can improve processing speed. The downside to that strategy is that you may have to trade off resolution (e.g. whole degrees only) to reduce table size.

A 2:1 mux only requires 3 gates, so there's not much to be gained by using a LUT.

2) can outputs of one set of look up tables be used to map SRAM bits of another look up table?

You can do whatever you want.

 

Sorry for not being clear.
let me rephrase
How can we implement a four variable function using only two input LUT?

If you start with two bits you can only get four possible results regadless of how may levels you go through.

 

Welcome to AAC!
The purpose of look-up tables is to simplify something and/or gain speed. For example a table with transcendental functions like sin, cos, tan. Instead of calculating them every time they occur, using a look-up table can improve processing speed. The downside to that strategy is that you may have to trade off resolution (e.g. whole degrees only) to reduce table size.

A 2:1 mux only requires 3 gates, so there's not much to be gained by using a LUT.
You can do whatever you want.

Thank you Dennis.
i am just asking this question for the sake of clearing my concept regarding LUT's.
with regards to my second question how can we implement four variable function using only two input LUT's?

 

with regards to my second question how can we implement four variable function using only two input LUT's?

I don't understand the question. What do you mean by 4 variable function? A 2 input LUT can only have 4 outputs. A 4 variable function can have more than 4 possibilities.

 

If you start with two bits you can only get four possible results regadless of how may levels you go through.

Can you show me how please? I am stuck after first level.

 

I don't understand the question. What do you mean by 4 variable function? A 2 input LUT can only have 4 outputs. A 4 variable function can have more than 4 possibilities.

That's what is confusing me.
According to some sources we can use 2 input LUT's in cascaded form to recognize a 4 variable function.

 

That's what is confusing me.
According to some sources we can use 2 input LUT's in cascaded form to recognize a 4 variable function.

also if as u said we can map the outputs of one group of LUT's onto SRAM of another LUT then i think we can do this using the following formation.

 

According to some sources we can use 2 input LUT's in cascaded form to recognize a 4 variable function.

More context would be helpful. What is the nature of this 4 variable function?

 

More context would be helpful. What is the nature of this 4 variable function?

it is any random four variable boolean function.

 

it is any random four variable boolean function.

Can't give any specific recommendations or reasons for such vague requirements.

 

Can't give any specific recommendations or reasons for such vague requirements.

Sorry if I am not being clear. Let me provide some pictures. Attached is picture and link of how we can realize 3 variable function using 2 input LUT's but i am not able to understand how this solution was derived.
https://electronics.stackexchange.c...e-input-lut-if-i-have-a-lot-of-two-input-luts

 

Sorry if I am not being clear.

Still doesn't make any sense to me. I started reading the link you provided, but decided it wasn't a good use of my time.

 

Sorry if I am not being clear. Let me provide some pictures. Attached is picture and link of how we can realize 3 variable function using 2 input LUT's but i am not able to understand how this solution was derived.
https://electronics.stackexchange.c...e-input-lut-if-i-have-a-lot-of-two-input-luts

So the diagram shows how using multiple LUTs you can implement various logic functions. You have to look at the contents of the boxes carefully. The one on the extreme right implements a Boolean .OR. function. This is often denoted with the same '+' plus symbol we use to mean addition. In programming languages we call this 'operator overloading'. The two boxes in the middel are implementing a Boolean .AND. function which is often indicated by the use of the '&' ampersand character. The dotted line box around the two .AND. boxes and the .OR. box is telling that such a combinatorial function perfoems the action of a 2:1 multiplexer.

I'm not quite sure how to interpret LUT1 & LUT2. It seems they implement a function of two variables, A and B, and a constant either 1 or 0. However the actual values of S and T are a mystery to me.

There are many was to implement a 2:1 multiplexer function. Your diagram uses 2 AND gates and 1 OR gate. Here is an example of a 2:1 multiplexer using 3 NAND gates.
A! and A2 are buffers where the output equals the input and the complementary output is unused. A3 is a combination buffer/inverter whose outputs are always the complement of each other. A4, A5, and A6 are all multi-input NAND gates. In this diagram, unused inputs are ignored.

 

Think of it this way…

A 4 input LUT has 16 different possibilities. Think binary. Four binary bits can represent 0 to 15; 16 possibilities.

A 2 input LUT can represent 4 different possibilities. If you take the output of a single LUT, and feed it into a second LUT plus the third input, you get 8 possibilities. Note that this second LUT is identical to the first.

Finally, feed this output to a third LUT with the fourth input, you get 16 possibilities.

Voila!