[SOLVED] Ans: 1. a) 2. a)
If we are asked second minimum, then 3 would do too.
The image is wrong, I mean, you just need one NOR/NAND to create a NOR/NAND function obviously, but other than that, I think this is the way.
I can't delete this question, please don't reply unless you see anything wrong. I really wanted to get rid of this question as it just serves the purpose of wasting my time and yours right now.
[SORRY FOR HAVING ASKED THIS QUESTION, I did try and solve it, but now my after a careful rewatch I learned I was mistaken]
1. What is the minimum number of nor gates required to implement a NOR function?
a) 1 b) 3
2. What is the minimum number of NAND gates required to implement a NAND function?
a) 1 b) 3
I think it's 1 for both questions, if 1 is not given then we go for the second minimum 3 NOR/NAND gates for 1 and 2 respectively
Designing a NAND gate using a combination of NAND gates and Designing a NOR gate using NOR, is this how you do it? (this was HW and the lecturer didn't bother to solve it or tell us the answer)
PS: I did try to look them up but I didn't get what I was looking for in the previously asked questions. I apologize if this was previously asked or if it's so easy and obvious.
If we are asked second minimum, then 3 would do too.
The image is wrong, I mean, you just need one NOR/NAND to create a NOR/NAND function obviously, but other than that, I think this is the way.
I can't delete this question, please don't reply unless you see anything wrong. I really wanted to get rid of this question as it just serves the purpose of wasting my time and yours right now.
[SORRY FOR HAVING ASKED THIS QUESTION, I did try and solve it, but now my after a careful rewatch I learned I was mistaken]
1. What is the minimum number of nor gates required to implement a NOR function?
a) 1 b) 3
2. What is the minimum number of NAND gates required to implement a NAND function?
a) 1 b) 3
I think it's 1 for both questions, if 1 is not given then we go for the second minimum 3 NOR/NAND gates for 1 and 2 respectively
Designing a NAND gate using a combination of NAND gates and Designing a NOR gate using NOR, is this how you do it? (this was HW and the lecturer didn't bother to solve it or tell us the answer)
PS: I did try to look them up but I didn't get what I was looking for in the previously asked questions. I apologize if this was previously asked or if it's so easy and obvious.
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