- Joined Jul 4, 2015
Resolved. Please close thread.
Sorry, my crystal ball is in the shop and I'm not a mind reader. You don't even tell us what answer you got, let alone show any work, but expect us to be able to tell where you went wrong???? Does that sound like a reasonable request?Pls refer to attached pic.
My working is as follows:
Since the current is sinking, the logic gate must be low. And since low voltage is defined as 1.5V so Vdd-1.5=3.5V. 3.5V is the output voltage. Sub in all the values to get t. Where did I get wrong?
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