I would put a resistor on this side of the diode to make sure that io pin isn't shot.

yes, something like that will work - and it works in some gate's output stages too.

you just need to make sure that you can live with the charge-up time set by the 500ohm resistor and the gate capacitance - again, not a problem for low frequency stuff we do.

i needed to clarify (gates between resistor and diode):

12v----resistor----diode----pic io pin
.....................|
.....................|
................fet gates

as for gate charge, it needs to be accounted for regardless of frequency. scope the gates @ PWM frequency to see the rise and fall times, etc. i typically drive high current brushless dc motors @ 30Hz and keep them at minimum 20-30% PWM after startup and drive them between startup-100% PWM. but as i mentioned before, the freqency chosen really depends on the characteristics of the motor.


the OP should also be weary of the flyback voltage and decaying oscillation between the motor coil and the fet's drain. the osciallation occurs due to motor inductor and fet's drain capacitance. with my setup i saw a 30kHz decaying ring so i squashed it with a small ceramic cap and resistor to ground. also had a 36v zener to help protect the fet, etc. without snubber you'll easily see this on the scope.

 

wow you guys posted alot of stuff while I was gone.

I read DC's post about darlington transistors, havent tried it yet, but did you mean something like this:

would this really work? it seems too simple..

 

a Microchip PIC18F1220/1320 can source/sink 25mA on its IO pins. so with 12v you can place a 500 ohm resistor (lowest you can go with 12v, etc) in series with a 1n4148 from +12v to the IO pin, and connect the fet gates between resistor and diode. when the IO pin totems low there is current being sinked and the fet gates should see about 0.7V. when the IO totems high current into the IO should stop and the fet gates should see 12v.

this design sounds like it is sinking the 12V through the 500ohm resistor to ground? wouldn't that fry the MCU?

 

this design sounds like it is sinking the 12V through the 500ohm resistor to ground? wouldn't that fry the MCU?

e/r=i

12v/500ohm=0.024A=24mA

as i mentioned earlier, the PIC18 i listed can source/sink 25mA on its IO pins. what is the current capacity of your MCU's IO pins (or the pin you are using for PWM)? what type of output stage does your PWM pin deploy?

 

did you mean something like this:

would this really work? it seems too simple..

nope, tie the fet gates to the npn collector, and Q2 emitter to ground. but simple it is.

just keep in mind the fet gates are being driven low when your PWM is high, etc.

also, anything in your PIC's datasheet that says you cannot float the IO pin? if so then tie a 10k resistor from the PWM pin to ground. this schematic (pending the changes) is safer than sinking current into the PIC, etc.

another note: this schematic will run the fans at 100% if the pic PWM fails in a low state. and if the PWM fails in a high state the fans will be stuck off. depending on what the application is, you can place a toggle switch between the darlington and R1, then tie the fet gates bewteen R1 and switch, this way if you need to override the semiconductors you can toggle the switch open and the fet gates will see full 12v, etc.

 

e/r=i

12v/500ohm=0.024A=24mA

as i mentioned earlier, the PIC18 i listed can source/sink 25mA on its IO pins. what is the current capacity of your MCU's IO pins (or the pin you are using for PWM)? what type of output stage does your PWM pin deploy?

yeah I understand, i did the math for that when you mentioned 500ohm was the smallest I should use for 12V.

but I am using a PIC18F2480, and the datasheet on page 419 says:

Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)

source: http://www.kip.uni-heidelberg.de/~gebelein/teaching/quadrocopter/doc/PIC18.pdf

that pretty much says that I cant put 12V on the pin.

 

ok, stick with the darlington topology (pending the changes i suggested in post #25), however, i would use a small logic level nFET in place of the darlington. then connect pic to this small fet like this:

pic io out-------------fet gate
..................|
.................10k
..................|
.................gnd

this yields "no" current on the io pin, etc.

 

the darlington topology will never work, for a few reasons:

1) there is no current path for the npn transistors to turn on.
2) there wouldn't be enough voltage drop on the g-s section to turn on the mosfet fully.

either your use a logic level mosfet, or you use a level shifter to isolate the mcu pins.

 

millwood,

if I use the n channel logic level mosfet, where should I connect the gates of my power mosfet? to the drain or the source?

 

the darlington topology will never work, for a few reasons:

1) there is no current path for the npn transistors to turn on.
2) there wouldn't be enough voltage drop on the g-s section to turn on the mosfet fully.

either your use a logic level mosfet, or you use a level shifter to isolate the mcu pins.

with the changes i suggested in post #25 the darlington setup will work just fine.

the emitter to ground and the power fets gates connected to the collector. when the npn base gets driven high the npn will conduct and the collector will look like ground.

if a fet is used instead of bjt then it gets connected the same way. R1 to logic fet drain, logic fet source to ground, power fet gates to logic fet drain. a fet solution means very little current in/out of the pwm pin.