I've been working through these simple examples and made a tiny change to the source and get weird errors.

This is the source:

// Project F: Hello Arty B - Top
// (C)2020 Will Green, open source hardware released under the MIT License
// Learn more at https://projectf.io

`default_nettype none
`timescale 1ns / 1ps


module top (
    input wire logic [3:0] sw,
    input wire logic [3:0] btn,
    output     logic [3:0] led
    );

    always_comb begin   
        if (btn[0] == 1) begin
           led[0] = sw[0];
           led[1] = sw[1];
           led[2] = sw[2];
           led[3] = sw[3];
        end      
    end
endmodule

This seemed to be a simple change that I'd expect to work fine, but I get:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_IBUF[0]] >

btn_IBUF[0]_inst (IBUF.O) is locked to IOB_X0Y137
and btn_IBUF_BUFG[0]_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Can't understand how such a tiny change could lead to all these errors!

This source (before my edits) works fine:

// Project F: Hello Arty B - Top
// (C)2020 Will Green, open source hardware released under the MIT License
// Learn more at https://projectf.io

`default_nettype none
`timescale 1ns / 1ps

module top (
    input wire logic [3:0] sw,
    input wire logic [3:0] btn,
    output     logic [3:0] led
    );

    always_comb begin
        if (sw[0] == 0 && sw[1] == 1) begin
            led[3:0] = btn[0] ? 4'b1001 : 4'b0110;
        end else begin
            led[3:0] = 4'b0000;
        end
    end
endmodule

 

Still very puzzling, this code gens a slightly more concrete error message though:

`default_nettype none
`timescale 1ns / 1ps


module top (
    input wire logic [3:0] sw,
    input wire logic [3:0] btn,
    output     logic [3:0] led
    );

    always_comb begin    
        if (sw[0] == 1) begin
           led[3:0] = {btn[3],btn[2],btn[1],btn[0]};
           //led[1] = sw[1];
           //led[2] = sw[2];
           //led[3] = sw[3];
        end       
    end
endmodule

Which is "Port 'sw[0]' is assigned to PACKAGE_PIN 'A8' which can only be used as the N side of a differential clock input."

Yet the very same "if" test on sw[0] is present in the code that works!!

 

OK I see a pattern, the "if" is fine if it is not that simple expression, no idea what's going on but this builds fine:

`default_nettype none
`timescale 1ns / 1ps


module top (
    input wire logic [3:0] sw,
    input wire logic [3:0] btn,
    output     logic [3:0] led
    );

    always_comb begin   
        if (sw[0] == 1 && sw[1] == 1) begin
           led[3:0] = {btn[3],btn[2],btn[1],btn[0]};
           //led[1] = sw[1];
           //led[2] = sw[2];
           //led[3] = sw[3];
        end      
    end
endmodule

 

OK I see a pattern, the "if" is fine if it is not that simple expression, no idea what but this builds fine:

`default_nettype none
`timescale 1ns / 1ps


module top (
    input wire logic [3:0] sw,
    input wire logic [3:0] btn,
    output     logic [3:0] led
    );

    always_comb begin   
        if (sw[0] == 1 && sw[1] == 1) begin
           led[3:0] = {btn[3],btn[2],btn[1],btn[0]};
           //led[1] = sw[1];
           //led[2] = sw[2];
           //led[3] = sw[3];
        end      
    end
endmodule

 

This is solved, not having an "else" led the tools to start making assumptions which led to the errors...