Pulse Delay circuit

Thread Starter

Jorj

Joined Sep 30, 2015
19
Hey folks. I'm trying to find a pulse delay circuit - delay will be in the matter of 100uS offset from the input signal (adjustable +-100uS).
I found few 555 timer based pulse delay circuits but when I made a simulation with Multisim don't seems to be working.
I just found out other circuit and wonder maybe it could work? What is the component, it's unmarked not really sure, it says J210 based time delay but I had no success in finding such part.
20140317-1029344411-0.jpg
 

AnalogKid

Joined Aug 1, 2013
8,484
A pulse delay circuit based on two monostables needs two adjustments unless the incoming pulse width is guaranteed not to change. There is another approach that has only one adjustment, yet delays both edges of an incoming pulse no matter how wide the pulse is or if it is variable. This approach uses two simple CMOS gates, one to drive an R-C delay and one to regenerate the edges. According to post #1, the required delay range is from 0 us to 200 us (100 us +/-100 us). I can't draw schematics right now; here is the series circuit:
Input
Gate 1:CMOS inverter with hysteresis - 40106, 74HC14, etc.
20K pot from Gate 1 out to Gate 2 in
0.015 uF capacitor from Gate 2 in to GND
Gate 2 out: Output.

0 ohms = 0 delay
10K ohms = approx. 100 us delay
20K ohms = approx 200 us delay

ak
 

Thread Starter

Jorj

Joined Sep 30, 2015
19
Thanks for suggestions. Since the pulse width is adjustable I chose last suggestion by AnalogKid.
Seems that too high capacitance & resistance are not working together well. A resistor 10K can go with capacitor up to 6.8nF if the cap is for example 10nF the second gate doesn't trigger at all (too low input voltage i guess). This way I can get 100uS which should get me started.
If I still need to go higher I can probably add one more pair after to get additional 100uS.

delay.png
 

AnalogKid

Joined Aug 1, 2013
8,484
There is more asymmetry in both the first gate's output impedance and votage levels and the second gate's transition levels than I expected. Changing to a gate than does not have hysteresis, such as a 4011, should improve things, particularly the range of component values that give an output.

ak
 

Thread Starter

Jorj

Joined Sep 30, 2015
19
Strange but with 4011 I get the same results - 100uS is the maximum achievable delay. Could be due to Multisim perhaps.
It will still do the job. If I need more I guess I could add additional stage for 100uS + 100uS.
 
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