From time to time I see resistor networks used as pull-ups on buses (address, data), and am wondering if there is a recommendation as to where along the bus they should be physically placed.

 

From time to time I see resistor networks used as pull-ups on buses (address, data), and am wondering if there is a recommendation as to where along the bus they should be physically placed.

Depends on the length of the bus, load, impedance, frequency, technology (TTL, CMOS, open-collector, open-drain, tri-state), single ended, differential, etc.

Any bus is a transmission line. Hence you want to minimize noise, ringing, and reflections.

 

For very high frequency signals, rise and fall times become critical. You have to examine the effect of bus loading on the eye diagram, delay, clock jitter, etc.




https://www.onsemi.com/pub/Collateral/AND9075-D.PDF

 

From time to time I see resistor networks used as pull-ups on buses (address, data), and am wondering if there is a recommendation as to where along the bus they should be physically placed.

There is an additional reason for using them unrelated to where they are located. This occurs in a system with multiple bus controllers, for example a CPU and a DMA controller. The pullups enforce a deterministic bus state when either controller relinquishes the bus followed by some delay before the other controller acquires the bus. This prevents uncontrolled transitions on the bus during the delay.

 

It also depends upon the type of resistor !!
large values such as 10K or 100K , tend to be pullups to hold bus high if the driver is not , its not to critical on where these go,
normally near the driver

values of 100 ohm and lower tend to be for impedance matching, these tend to go at the receiver end,

As ever, there is a bunch of reasons a circuit could need a pull up ,
unfortunately its only by experience that you will recognise to a reasonable certainty from a schematic what each is doing ,

 

OK. The master clock on the two boards with buses is 1MHz, and the pull-up networks are 10K.

So on the I/O board, I'll keep the networks near the incoming bus drivers ('244 and '245) and on the logic board, I'll put both near the processor?

 

sounds good

hows the io board connected to the processor

just check you dont have two pullups on one line

 

The I/O board taps into part of the address bus and the full data bus, along with clock, R/W, and one select line.

On the I/O board, all three sets of signals pass through buffers before continuing to the rest of the circuitry. The address group passes through a '244 wired 'always on', as do the clock / control lines (half a '241). The data bus passes through a '245, and which has some address logic to control the direction of the data bus.

As for multiple pullups, it works out that there's one set on the logic board side and one on the I/O board side, the buffers being the dividing point.

 

sounds good,
just dont use ribbon cable betwwen them,

 

Oh? In the original equipment I'm copying / updating, the I/O board was connected to the logic board by way of a pair of 18-pin ribbon cables (the I/O was done as an add-on, patched in where the NVRAM chips resided).

I'm planning on using a header and socket to connect the two in the 'improved' version.

 

I was wondering,
How long the cable ?

So, Ribbon cable is very bad at taking high speed signals , unless precautions are taken

such as, in no particular order
use differential signals,
use end termination
alternate wires in the ribbon being ground
use slow rise / fall time logic
use series start termination

I've had 1m of ribbon being feed with TTL 5 have 19Volts spikes at the far end,
the far end did not last long.

Keep it as short as practical,
use scope to see what the far end looks like

 

I'd say about 10"?

My first attempt as a direct retrofit wasn't successful as a layout error resulted in me needing unequal length cable (one was 3" and the other 10"). As I said, I plan to go with mating headers between the logic and I/O boards, and I'm now thinking of moving the display / keyboard processor off the display board to the I/O board to shorten up the data bus run (in the original, the display and I/O boards were linked with another 10" ribbon cable with every other pin grounded, but I intend to use mating connectors instead as I'm going to respin all 6 boards).