I understand that it's 'a mystery' how the circuit will actually behave. The levels of actual V[in] & I[in] are unknown and can't be calculated (even from the info provided in datasheet).
We kind of 'rely' that the input will be pulled-up/down to HIGH/LOW (but to some actually 'unknown' level), based on calculation techniques for R values that worked previously fine in other designs.
Am I right ?

No. The datasheet gives a max current, when pulled up to 5.5V, and a max current when pulled to 2.4V, which is the minimum you would want to ensure the input is high. Any other voltage in that range will be somewhere in between, which is sufficient information to calculate a resistor that will guarantee a high logic level as well as a max current draw. There is no need to be concerned with anything else. So, no, we are not just guessing and hoping it will work.
Bob

 

We are engineers, not wizards. We design circuits to specifications given design data and criteria, not by looking into a crystal ball and making wild guesses.

This we are not:

 

We are engineers, not wizards. We design circuits to specifications given design data and criteria, not by looking into a crystal ball and making wild guesses.

I needed to understand how the 'magic' works
I think BobTPH's reply totally fixed my interpretation of this 'pull-x' issue.

The datasheet gives a max current, when pulled up to 5.5V, and a max current when pulled to 2.4V, which is the minimum you would want to ensure the input is high. Any other voltage in that range will be somewhere in between, which is sufficient information to calculate a resistor that will guarantee a high logic level as well as a max current draw. There is no need to be concerned with anything else. So, no, we are not just guessing and hoping it will work.

Thanks all for investing time to explain

 

Interesting thread on the problem -

https://electronics.stackexchange.c...tor-pull-up-down-standard-for-74-series-chips


Regards, Dana.