I am having a problem when I tried to simulate the frequency divider. Here's what I designed:
View attachment 246792
and here is the simulation:


it's pretty basic design. However, where did I make the mistake. I tried to add 999k in seriers resistor behind output and replace 7474 with 74hc and 74als but it didnt help.
Thank you for the help!

 

I get 'page not found' for your attachment.

 

 

Hello,

To start with, you are using a digital chip to process an analog signal.
The digital chip can not work on the negative part of the signal.
Also the rise and fall times are to slow from the analog signal.
First process the analog signal to have a digital signal for the D-flipflop.
This can be done using a comparator or schmitt trigger circuit.

Bertus

 

Yeah. Flip-flops like the 7474 don't work with CLK inputs that are sinewaves that swing between +5V and -5V. Try a square wave that goes between 0V (GND) and +5V. Where did you learn about TTL devices? If it was an online resource, I'd like to help the author clarify his information.

 

I tried the square wave clock. here is the circuit and simulation.

 

The LM393 has an open collector output and REQUIRES a pullup resistor to Vcc (+5V). 1.6 Volts does not make a logic '1' -- sorry. The TTL CLK input is actually sourcing current into the output impedance of the comparator.
I think going back to some basic introductory material on TTL circuits would be a great idea.
It's hard to beat free!
TTL Cook Book : Don Lancaster : Free Download, Borrow, and Streaming : Internet Archive

 

Sure, thanks

 

Sure, thanks

No problem.

 

Hello,

An other book of interest might be:
ti :: Texas Instruments Electronics Series :: Morris Designing With TTL Integrated Circuits 1971

Bertus