Hi guys, i am really unsure of how to tackle this question .
Calculate the approximate propagation delay.
My working would be (0.1 x 10^-10)(3.5 - 1.5)/(0.1 x 10^-3)
i got 3.5 as the minimum voltage for a CMOS inverter to be on a high state and the 1.5 as the maxmimum voltage for a CMOS inverter to be on a low state. Would this working be correct?
A CMOS inverter, operating from a 5V power supply, drives a second inverter which has a
gate capacitance of 0.1pF. The current in the saturation region is I
gate capacitance of 0.1pF. The current in the saturation region is I
D ≈ K (VGS‐VT)2 = 0.1mA,
the propagation delay is tP = C ΔV/ID, and the dynamic power is PD = S f C V2.
the propagation delay is tP = C ΔV/ID, and the dynamic power is PD = S f C V2.
Calculate the approximate propagation delay.
My working would be (0.1 x 10^-10)(3.5 - 1.5)/(0.1 x 10^-3)
i got 3.5 as the minimum voltage for a CMOS inverter to be on a high state and the 1.5 as the maxmimum voltage for a CMOS inverter to be on a low state. Would this working be correct?