It's the minimum amount of time that D needs to be stable before the flip flop is clocked. If it was 0ns, they would have said that.I’ll have to confess that I’m not knowledgeable enough to understand what’s meant by set up time.
Guess again. They have the same delay; same RC and the propagation delay through an inverter. Since both inverters are in the same package, the delays will be as matched as you can get. In any case, there's no way there'll be a 25ns difference.That said surely the phase difference between the signals arriving at D and the clock ensure way more than 25nS?
Then you should use the same gate that's clocking the flip flop.But going back to the output of U2A what I meant was that it’s not debounced in any way so whichever AND gate is set high on its other input from the flip flop will get a potentially ‘dirty’ input on its other gate.