Problem using rotary encoders to clock binary counter

Thread Starter

paulski

Joined May 5, 2020
14
A little while back I assembled a test board to check I could get clean pulses from a couple of mechanical rotary encoders using some simple debouncing and logic to also get separate outputs for each direction plus an output for the push switch of one. The schematic is attached. When I check the outputs on the scope they look perfectly clean with one pulse for each detent. However, when I incorporated this into a circuit that uses 74HC193 synchronous up/down counters I get increments / decrements of one or more (usually more) than one for each pulse. I'm really stuck on this and even tried using the pulses to clock a breadboarded CD4040 circuit - same result, it counted up sometimes one more often more than one for each pulse.

I know rotary encoders can be a pain to get clean pulses but my scope shows the pulses are just that so I'm at a loss to figure this out. I'm hoping somebody here can give me a pointer as to where the problem might lie.

The test board:

IMG_2477.JPG
 

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dl324

Joined Mar 30, 2015
10,758
How is this circuit supposed to clock 74HC193? One clock input needs to be HIGH before the other will be active. In your circuit, either Up or Down is LOW and the other toggles.
clipimage.jpg

Are you mixing 74LS and 74HC logic? 74LS isn't guaranteed to drive 74HC.
 

AnalogKid

Joined Aug 1, 2013
8,467
The schematic in post #1 has a significant problem. It shows three encoders' outputs connected directly together. This means that, depending on the positions of two of the encoders, both signal lines are connected to GND all the time and rotating the other encoder does nothing.

ak
 

Thread Starter

paulski

Joined May 5, 2020
14
How is this circuit supposed to clock 74HC193? One clock input needs to be HIGH before the other will be active. In your circuit, either Up or Down is LOW and the other toggles.
View attachment 206402

Are you mixing 74LS and 74HC logic? 74LS isn't guaranteed to drive 74HC.
All the parts used in the above are the 74HC versions, KiCad's parts library doesn't have all of them and I forgot to change them. The context for the circuit is shown in the schematic attached - the pulses from the sub-circuit are inverted before going to the 74HC193's clock inputs.
 

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Thread Starter

paulski

Joined May 5, 2020
14
The schematic in post #1 has a significant problem. It shows three encoders' outputs connected directly together. This means that, depending on the positions of two of the encoders, both signal lines are connected to GND all the time and rotating the other encoder does nothing.

ak
The three 'paralleled' encoders represent three possible locations on the PCB, only one is fitted.
 

dl324

Joined Mar 30, 2015
10,758
The context for the circuit is shown in the schematic attached - the pulses from the sub-circuit are inverted before going to the 74HC193's clock inputs.
Even though you say you're seeing the expected debounced switch contacts on your scope, you must have a switch bounce problem. If you can't get your scope to show you the problem, are you debugging this on a breadboard? Or the board you showed in your first post?

I think you should confirm that it's a switch bounce problem by putting a one shot on the encoder outputs.
 

Thread Starter

paulski

Joined May 5, 2020
14
Even though you say you're seeing the expected debounced switch contacts on your scope, you must have a switch bounce problem. If you can't get your scope to show you the problem, are you debugging this on a breadboard? Or the board you showed in your first post?

I think you should confirm that it's a switch bounce problem by putting a one shot on the encoder outputs.
I'm in the middle of replacing my old 'scopes with a new Rigol which will hopefully be with me tomorrow. Whether this lets me see the issue any better remains to be seen. I've been debugging this in the main circuit and also by running the test board as shown into a breadboarded circuit. Both cases produce the same undesired result.

That aside I like the idea of a one shot to test the issue. The only problem I can see with that if I had to use it to resolve the issue might be that the pulse widths from the encoder circuit vary greatly with the speed of rotation. I'd like to be able to spin the volume control quickly and have it register each detent and so I'd guess I'd need to have an output pulse width from the one shot that was shorter than the input pulses. I think I'm right is saying that can be done with a non-retriggerable one shot and suitable RC values?
 

dl324

Joined Mar 30, 2015
10,758
The only problem I can see with that if I had to use it to resolve the issue might be that the pulse widths from the encoder circuit vary greatly with the speed of rotation. I'd like to be able to spin the volume control quickly and have it register each detent and so I'd guess I'd need to have an output pulse width from the one shot that was shorter than the input pulses.
The datasheet said contact bounce at 15RPM was 2ms. I'd fiddle with the oneshot time period until it fixed the problem, then tweak the R and C you're using for filtering now.
 

Thread Starter

paulski

Joined May 5, 2020
14
hi paul,
You have a 'race' condition at the AND gate inputs, try this option, try adding adding R3 and C5.
E
Hi Eric,
Thanks for this, last night I realised that whilst I’d filtered the outputs driving the clock / data of the flip flop I hadn’t filtered the output driving the AND gate! I haven’t had time to fully absorb your reply yet but I think that’s what your suggesting doing. It occurs to me that I’m missing the RC in exactly the pace it’s most needed!
 

ericgibbs

Joined Jan 29, 2010
10,058
hi Paul,
The Quad Waveform sketch on the datasheet is IMO poorly drawn, this is what I see for the Encoder circuit they show, which matches a encoder on the bench.
Modified image.
E
For Ref: Added. Sim of Up/Down
 

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dl324

Joined Mar 30, 2015
10,758
last night I realised that whilst I’d filtered the outputs driving the clock / data of the flip flop I hadn’t filtered the output driving the AND gate!
clipimage.jpg
I don't see any problems with the AND gate inputs. The output from U2A has less propagation delay than the signals from U2B and U2C going through U3A to get to the AND gates. So the inputs on U1A-1 and U1B-4 are stable before U3A data propagates to the outputs.

I'd be more worried about having sufficient setup time on the D input of U3A before it gets clocked. The datasheet specifies a minimum setup time of 25ns and your circuit doesn't provide that.
clipimage.jpg
clipimage.jpg

EDIT: Added schematic for relevant components and datasheet specs.
 
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Thread Starter

paulski

Joined May 5, 2020
14
View attachment 206553
I don't see any problems with the AND gate inputs. The output from U2A has less propagation delay than the signals from U2B and U2C going through U3A to get to the AND gates. So the inputs on U1A-1 and U1B-4 are stable before U3A data propagates to the outputs.

I'd be more worried about having sufficient setup time on the D input of U3A before it gets clocked. The datasheet specifies a minimum setup time of 25ns and your circuit doesn't provide that.
View attachment 206552
View attachment 206551

EDIT: Added schematic for relevant components and datasheet specs.
I’ll have to confess that I’m not knowledgeable enough to understand what’s meant by set up time. That said surely the phase difference between the signals arriving at D and the clock ensure way more than 25nS?

But going back to the output of U2A what I meant was that it’s not debounced in any way so whichever AND gate is set high on its other input from the flip flop will get a potentially ‘dirty’ input on its other gate.
 
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