I’ll have to confess that I’m not knowledgeable enough to understand what’s meant by set up time.

It's the minimum amount of time that D needs to be stable before the flip flop is clocked. If it was 0ns, they would have said that.

That said surely the phase difference between the signals arriving at D and the clock ensure way more than 25nS?

Guess again. They have the same delay; same RC and the propagation delay through an inverter. Since both inverters are in the same package, the delays will be as matched as you can get. In any case, there's no way there'll be a 25ns difference.

But going back to the output of U2A what I meant was that it’s not debounced in any way so whichever AND gate is set high on its other input from the flip flop will get a potentially ‘dirty’ input on its other gate.

Then you should use the same gate that's clocking the flip flop.

 

switch debouncing,
many many circuits out there,
just do a search,

In this sort of case Id be looking at a rotary decoder IC that has the logic built in , or do the debounce in a processor / fpga ,

https://www.best-microcontroller-projects.com/rotary-encoder.html

https://www.elmelectronics.com/wp-content/uploads/2016/07/ELM401DS.pdf

 

It's the minimum amount of time that D needs to be stable before the flip flop is clocked. If it was 0ns, they would have said that.
Guess again. They have the same delay; same RC and the propagation delay through an inverter. Since both inverters are in the same package, the delays will be as matched as you can get. In any case, there's no way there'll be a 25ns difference.
Then you should use the same gate that's clocking the flip flop.

Re the phase difference I was referring to the 90 degrees quadrature difference between the two encoder outputs.

Using the same gate that is clocking the flip flop to drive the second input to the AND gate has largely resolved the issue. Also increasing the filter caps to 100nF improves things further. It's still not 100% perfect as there's occasionally a glitch. I'll try 220nF of capacitance when I have them on hand to see if that helps.

 

It's still not 100% perfect as there's occasionally a glitch. I'll try 220nF of capacitance when I have them on hand to see if that helps.

If you want it to be 100%, you need to get serious about finding out what's causing the problem and fix it in a robust way. If you insert a one shot, you can confirm or deny that it's a glitch filtering problem.

The RC approach is a hack because it depends on the threshold voltages of the Schmitt input. A debounce circuit like MC14490 or a one shot is a more robust solution.

These are the specs for Nexperia 74HC14:

The variation in threshold voltages is up to 1.45V and 1.1V for positive and negative thresholds at Vcc=4.5V, respectively.