Preventing saturation in a boost converter in continuous mode

Thread Starter

Robin66

Joined Jan 5, 2016
275
Hi, I’m wondering if anyone has any ideas that might help me. I’m working on a 20V - > 20-40V boost converter. I’ve run into difficultly recently by saturating my 10uH inductor, which will happen at ~25A. In continuous mode I have no idea in which way the avg and peak L1 current is trending. I’d like to introduce some direct current sensing method so that I can achieve maximum power transfer through the converter while maintaining good efficiency. So far the best solution I’ve come up with is introducing a hall sensor to GND in series with L1. ACS712ELCTR-20A-T is on my radar because it’s rated to 20A. Other ideas I’ve considered are:
  • Measuring the initial dV/dt of the FET’s parasitic drain-source capacitance when the charge phase ends. dV/dt here would be ~1V/ns so it’d be necessary to have some sort of peak detect circuit of a capacitor and diode to allow an ADC to derive the dV/dt. I suspect the error terms would be very large and it would be necessary to add a 10nF fixed capacitor across Source-Drain due to the variability of the FETs capacitance.
  • Measuring the initial dV/dt across the output capacitor C1 as L1 discharges into it. dV/dt here would be ~0.01V/us so is measurable directly by the ADC. The capacitance is better known but still varies with temp. and the current sinked by the output can vary and cause error.
  • Adding an enameled strand around L1's core and measure the induced voltage which should round off as saturation starts. No idea how I'd determine this though.
Are there any neat tricks people have employed with success to prevent saturation, or is the hall sensor my best bet?

boost-converter-basic-cct.gif
 

ian field

Joined Oct 27, 2012
6,536
Hi, I’m wondering if anyone has any ideas that might help me. I’m working on a 20V - > 20-40V boost converter. I’ve run into difficultly recently by saturating my 10uH inductor, which will happen at ~25A. In continuous mode I have no idea in which way the avg and peak L1 current is trending. I’d like to introduce some direct current sensing method so that I can achieve maximum power transfer through the converter while maintaining good efficiency. So far the best solution I’ve come up with is introducing a hall sensor to GND in series with L1. ACS712ELCTR-20A-T is on my radar because it’s rated to 20A. Other ideas I’ve considered are:
  • Measuring the initial dV/dt of the FET’s parasitic drain-source capacitance when the charge phase ends. dV/dt here would be ~1V/ns so it’d be necessary to have some sort of peak detect circuit of a capacitor and diode to allow an ADC to derive the dV/dt. I suspect the error terms would be very large and it would be necessary to add a 10nF fixed capacitor across Source-Drain due to the variability of the FETs capacitance.
  • Measuring the initial dV/dt across the output capacitor C1 as L1 discharges into it. dV/dt here would be ~0.01V/us so is measurable directly by the ADC. The capacitance is better known but still varies with temp. and the current sinked by the output can vary and cause error.
  • Adding an enameled strand around L1's core and measure the induced voltage which should round off as saturation starts. No idea how I'd determine this though.
Are there any neat tricks people have employed with success to prevent saturation, or is the hall sensor my best bet?

View attachment 125430
Core saturation usually means your inductor is too small.

You can put a current sense resistor in the MOSFET source and use the voltage developed to switch on a BJT - the BJT shunts the gate drive and arrests the current rise. By the time you've worked out the values to prevent the current rise going exponential and punching the MOSFET through - you won't be able to get as much power through and have to use a bigger inductor anyway.
 

Thread Starter

Robin66

Joined Jan 5, 2016
275
I like the direct approach of the BJT shunt, but to hit 0.6V drop near saturation it'll be dropping 0.3V typically with moderate load which (I hope) would dwarf all the other drops in the high current path (it's a synchronous converter, so there's a second FET across D1).
Core saturation usually means your inductor is too small.
If used optimally I'm pretty confident that L1 is big enough if I sort out my switching times. For example, if at max power I keep the avg current at 15A (start charge at 10A, start discharge at 20A) and Vin = 20V and Vout = 40V so tCharge == tDischarge, then the output is 15A * 50% * 40V = 300W. I could squeeze the headroom on saturation a bit more and increase the switching rate to get this up to 400W which is plenty. Please correct me if these calcs appear dubious
 

ian field

Joined Oct 27, 2012
6,536
I like the direct approach of the BJT shunt, but to hit 0.6V drop near saturation it'll be dropping 0.3V typically with moderate load which (I hope) would dwarf all the other drops in the high current path (it's a synchronous converter, so there's a second FET across D1).
You need about 15R or more between the source current sense resistor and the BJT base, otherwise the spike at the onset of core saturation will rip the B/E junction out. The BJT collector must clamp out the gate drive so the saturated core can recover.

In a self oscillating switcher; shortening the on time will increase the frequency slightly. A fixed frequency PWM drive will introduce some dead time.

Current sensing is to prevent saturation - not regulate it. Working it out can provide more information on selecting the right size inductor, or determining the frequency you need for the one you have.
 

Thread Starter

Robin66

Joined Jan 5, 2016
275
Cool, thanks a lot. This has been helpful. It hadn't occurred to me that blowout would be so sudden but it makes sense now considering that at saturation the effective L will become ~0
 
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