In the above circuit if clock(CLK 1) goes from 0 to 1 and input D =0 ,this makes Q=0.
It is stated that when the clock is at HIGH(1) any further change in input does not affect output,how it is so .Can you explain me please.Thank you in advance

 

Look here
http://www.play-hookey.com/digital/alt_flip_flops/d_nand_flip-flop.html
http://homepages.cae.wisc.edu/~ece352/spring00/handouts/flipflop.pdf
Any more questions ?

 

nice link .But for confirmation see this image
My doubt start at very beginning.I have added notation to the image and uploaded, see this image
Consider clk 1(transfered from 0 to 1) and input data =0
In the image what is the input value for A nand gate and C nand gate.For clearance i marked that line with red.how to predict that input values.Please explain me that part.Thank you

 

In this type of a circuit you need to know the past.
Before CLK transfer from 0 to 1 we have 0 at CLK.
So we have this situation
http://forum.allaboutcircuits.com/attachment.php?attachmentid=72085&stc=1&d=1409063200
Notice that we still don't know Q and /Q state.
But now if CLK transient from 0 to 1 we have all the info.
http://forum.allaboutcircuits.com/attachment.php?attachmentid=72086&stc=1&d=1409063230
Gate C will change his state from 1 to 0.
And gate F will set 1 at /Q and thanks to this 1 at F output gate E will set 0 at Q output.

 

Thanks .its clear now

 

I'm glad to hear that.