Has anyone ever seen this configuration? I want to find the conditions to have all devices in saturation and have the circuit operating like a cascode current mirror. I cannot seem to find much information on this kind of configuration.

 

If You will do an Internet-Search, You can spend all day going over various Current-Mirror designs.

It would help if You would state what it is that You are trying to accomplish,
and why You particularly want a Cascode-Configuration.
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If You will do an Internet-Search, You can spend all day going over various Current-Mirror designs.

It would help if You would state what it is that You are trying to accomplish,
and why You particularly want a Cascode-Configuration.
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I want to find the conditions of the devices to get all devices in saturation

 

Is this a Homework question ?
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Is this a Homework question ?
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Yes, the question is “size the transistors so that each transistor is biased in saturation. What are the golden conditions that put each transistor in saturation and has the circuit behaving like a regular cascode current mirror ?” I tried adjusting the size of N5 and N8 so that the source voltage is larger, hence increasing the drain voltage of the mirror devices

 

With the FETs in "Saturation",
the Circuit will not be performing as a Current-Mirror of any type or configuration.

This sounds like a trick question to see if You are paying attention and
understanding what is supposed to be occurring in this Circuit,
and possibly, what the condition of "Saturation" means.
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If you are not aware, the saturation definition for a FET is different than for a BJT.

 

With the FETs in "Saturation",
the Circuit will not be performing as a Current-Mirror of any type or configuration.

This sounds like a trick question to see if You are paying attention and
understanding what is supposed to be occurring in this Circuit,
and possibly, what the condition of "Saturation" means.
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[/QUOTE
That’s what I was thinking, shouldn’t the upper transistors be in triode region?

If you are not aware, the saturation definition for a FET is different than for a BJT.

yes I know, these are FETs

 

yes I know, these are FETs

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OK, Fine,
now tell us what the requirements are to have a FET in Saturation.

And then note that all of the FETs have their Gates connected together,
but the various Sources and Drains are at different potentials from Ground.
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OK, Fine,
now tell us what the requirements are to have a FET in Saturation.

And then note that all of the FETs have their Gates connected together,
but the Sources and Drains are at different potentials from Ground.
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Vds > vgs-vth. But if all the gates are equal to the drain of N5, where does that leave me?

 

That's why I said that it looks like a trick-question.

But don't get me wrong,
I ,literally, don't know what I'm talking about in this case.

I had to look-up the definition of Saturation, as I never use the term, or definition,
but I'm just a Genius-Hobbyist who's reasonably good at
interpreting performance-graphs in a Spec-Sheet,
not a proffesional EE.

It looks to me like an impossible conundrum,
which can never result in a stable condition, as outlined in the original question,
but I could be missing something.
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The cascade arrangement for differential pair is sort of related. Just talking about CC.
A discussion of constant current using n-enhancement mosfet shown in the video is slightly mathematical,
the formula uses square root. When you see the simulation results the accomplished goal of CC circuit is shown.

 

I wish this discussion had gotten more into the supposed
"length" and "width" discrepancies typically found in MOSFETs,
and any trends regarding the other usual FET specifications that
might be expected to be found to "usually" have "more", or "less", "length", and "width", discrepancies.

And, are the usual discrepancies normally found to be in the ~0.01% range, or the ~10%+ range.
Instead, these known discrepancies are completely ignored and "Zeroed-Out" in the presented calculations.
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