Hello everyone, I have recently started studying MOSFETs.
I would like to ask you if this type of design makes sense (I haven't seen it anywhere! It is my own draft, written so we can discuss it together).

Let's assume:
- PMOS (Q2): Vds,max = 100V , Vgs = [-20 .. 20]V e Rds,on = 0.3ohm
- NMOS (Q1): something less powerful of Q2 (not relevant in this example)

When the logic is 1, there should be no problem because PMOS closes and 50V passes through. Right?

When the logic is 0, it seems to me that above 10k, 50V (Vin) passes through the Zener diode. Right?
If so, isn't it a bit 'risky' to rely only on that Zener diode? If something happens on it, Q2 gate risks remaining floating.

In short, I await your comments that 'debunk' this design idea.



Thanks!

 

There should be a pullup resistor on Q2's gate. Otherwise it will float into a partially-on state and Q2 fail when current goes through it. What happens when there is no pullup depends on whether the zener has more leakage than the body diode of Q1, and I wouldn't like to guess.

 

If so, isn't it a bit 'risky' to rely only on that Zener diode?

Yes.
You identified a problem, so why didn't you fix it in your design?

If it's not clear, the pullup resistor goes in parallel with the Zener.

 

There should be a pullup resistor on Q2's gate. Otherwise it will float into a partially-on state and Q2 fail when current goes through it. What happens when there is no pullup depends on whether the zener has more leakage than the body diode of Q1, and I wouldn't like to guess.

Yes.
You identified a problem, so why didn't you fix it in your design?

If it's not clear, the pullup resistor goes in parallel with the Zener.

Thanks!
1) What should be the value of the new pull-up resistor? 1K? 10k? Does it affect the switching time of Q2 with its parasitic capacitance Cgs?

2) At this point, does it make sense to leave the Zener diode there? Can I replace it with an Rpull-up?

 

1) What should be the value of the new pull-up resistor? 1K? 10k? Does it affect the switching time of Q2 with its parasitic capacitance Cgs?

10k is a common, nominal value to use.
The switching time will not be noticeable degraded for this application.

2) At this point, does it make sense to leave the Zener diode there? Can I replace it with an Rpull-up?

Yes, you can select the resistor values to limit the Vgs below MOSFETs max rating, but still sufficient to fully turn-on the MOSFET.
Whether this works depends upon how large a variation in the input voltage you need to design for.

 

10k is a common, nominal value to use.
The switching time will not be noticeable degraded for this application.
Yes, you can select the resistor values to limit the Vgs below MOSFETs max rating, but still sufficient to fully turn-on the MOSFET.
Whether this works depends upon how large a variation in the input voltage you need to design for.

Thanks for the response.
I still have a doubt: what could a Zener diode be used for there (between the gate and source of the PMOS)?
I put it in because I thought it would protect against possible overvoltage of V_IN (i.e. with a breakdown voltage lower than Vgs max), but maybe I'm wrong and it doesn't make sense.

 

I still have a doubt: what could a Zener diode be used for there (between the gate and source of the PMOS)?
I put it in because I thought it would protect against possible overvoltage of V_IN (i.e. with a breakdown voltage lower than Vgs max), but maybe I'm wrong and it doesn't make sense.

The gate voltage information you provided was the maximum. So the zener diode would prevent the G-S voltage from exceeding 12V when the MOSFET was turned on.

 

The gate voltage information you provided was the maximum. So the zener diode would prevent the G-S voltage from exceeding 12V when the MOSFET was turned on.

10k is a common, nominal value to use.
The switching time will not be noticeable degraded for this application.
Yes, you can select the resistor values to limit the Vgs below MOSFETs max rating, but still sufficient to fully turn-on the MOSFET.
Whether this works depends upon how large a variation in the input voltage you need to design for.

Now that I look again at the photo in my post, if LOGIC input = 0, NMOS Q1 is off and there is no V_IN above R42, but there is V_IN - Vzener?
..I'm getting confused

 

Now that I look again at the photo in my post, if LOGIC input = 0, NMOS Q1 is off and there is no V_IN above R42, but there is V_IN - Vzener?

Which resistor is R42? Is there now a resistor in parallel with the zener diode?

 

Which resistor is R42? Is there now a resistor in parallel with the zener diode?

Sorry! I got confused.
I "deleted" my post number #8.

My question regarding your comment is: should I choose a Zener diode with a zener voltage equal to the maximum Vgs that the PMOS Q2 can withstand?

I had set it to 12V, but if Vgs = [-20 .. 20]V then perhaps I should choose 20V max (?)

 

My question regarding your comment is: should I choose a Zener diode with a zener voltage equal to the maximum Vgs that the PMOS Q2 can withstand?

I wouldn't do that. But it depends on the current required and the MOSFET. I checked a datasheet for IRF9540, which also has a Vgs(max) of 20V, and they only characterized it for up to VGS=-10V. Including absolute max continuous drain current at that voltage.

 

should I choose a Zener diode with a zener voltage equal to the maximum Vgs that the PMOS Q2 can withstand?

No.
That would just unnecessarily stress the gate oxide.
There's no reason to use a Zener voltage higher than 10V, since there is no significant reduction in the MOSFET on-resistance above that voltage.