The PMOS and NNOS symbols in the Figure 1 in the following link is wrong ?

https://www.allaboutcircuits.com/te...structure-and-operation-for-analog-ic-design/

Is the following true ?

PMOS: The gate (channel) is P Type
NMOS: The gate (channel) is N Type

 

That is a hopeless article. Why introduce the symbols, and then on the same page use completely different symbols?
The symbols lower down the page (not those in figure 1) are probably the most correct, but there are many short-cut symbols out there.
A solid line between drain and source (as in figure 1) should indicate a depletion mode device, the SPICE symbols of figures 4 and 5, with a broken line between drain and source should indicate enhancement mode devices.

 

The PMOS and NNOS symbols in the Figure 1 in the following link is wrong ?

Image in question:

They're correct and I don't like them.

I learned about them while I was reading some information from college courses. Have no idea how they differentiate between enhancement and depletion mode devices.

Is the following true ?

PMOS: The gate (channel) is P Type
NMOS: The gate (channel) is N Type

Yes.

P type devices are made by diffusing a p-type dopant (usually Boron) into an n-type silicon substrate. N type devices are made by diffusing an n-type dopant (phosphorous or arsenic) into a p-type sililcon substrate.

 

Image in question:
View attachment 323473
They're correct and I don't like them.

since when? Infineon (International Rectifier) is still using the one I’m used to, and they should perhaps know a thing or two about MOSFETs.
(and I completely agree with you about the depletion/enhancement thing)

 

Undated college material:

 

Thanks for your comments.

In MOFET devices, the channel is established between Drain and Source when a certain voltage is applied at the Gate, is that true ?

The channel is made of P-Type material in PMOS and the channel is made of N-Type material in NMOS, right ?

 

Image in question:
View attachment 323473
They're correct and I don't like them.

I learned about them while I was reading some information from college courses. Have no idea how they differentiate between enhancement and depletion mode devices.
Yes.

P type devices are made by diffusing a p-type dopant (usually Boron) into an n-type silicon substrate. N type devices are made by diffusing an n-type dopant (phosphorous or arsenic) into a p-type sililcon substrate.

Figure 1 is wrong ?
Figure 4 and Figure 6 are ok ?

 

Figure 1 is wrong ?
Figure 4 and Figure 6 are ok ?

I said the symbols in figure 1 are correct. As are the symbols in figs 4 and 6.

In MOFET devices, the channel is established between Drain and Source when a certain voltage is applied at the Gate, is that true ?

In enhancement mode devices, that's the case for discrete devices. In integrated circuits, leakage current became a large problem at around 90nm. In one of our microprocessors, it was calculated that transistors that were off accounted for a significant portion of overall power dissipation.

In depletion mode devices, a channel exists with no gate bias (much like JFETs). You can make the intrinsic channel larger or smaller by applying appropriate gate bias (this doesn't work with JFETs).

The channel is made of P-Type material in PMOS and the channel is made of N-Type material in NMOS, right ?

Was what I said on post #3 not clear?

 

I found another link.

https://madpcb.com/glossary/enhancement-mode-mosfet/

The symbols in this link are shown for NMOS and PMOS for both Depletion and Enhancement mode.

 

The symbols in this link are shown for NMOS and PMOS for both Depletion and Enhancement mode.

Those are the commonly used symbols. The question I had was how do they indicate depletion mode devices using the style in figure 1.

 

Few designers work with different kinds of transistors in the same design, so the need to distinguish between the different types is seldom important. As a consequence, many designers use the same transistor symbol for any kind of FET transistor. It's far more common to see FET and BJT devices in the same design, so there is a practical need to distinguish between them, otherwise you would probably see the sloppiness extended to the point of using just two generic transistor symbols regardless of technology (the two being used to only distinguish P and N variants).

In the days of hand drawn schematics (and even today, since hand sketched schematics are widely used at many points in the design process), the value of being able to quickly and easily draw the symbol simply outweighed the value of the fine distinctions that didn't matter in the end since the type of transistor being used was fixed. In cases where different types of FETs were used, designers usually made the effort to use different symbols or at least annotate the schematics appropriately.

For logic designed, the NFET/PFET symbols are often simplified to just:



This makes for a very clean schematic, abstracting all of the extraneous details, such as bulk connections, away. It is also a good mental match to the "bubble logic" that logic designers tend to think in terms of.