Hello, the pipeline of MIPS processor is consisted from five stages : IF ID EXEC MEM WR
my question is, if I've instruction like "halt" or "add"(doesn't need memory) ..will it pass from all the stages and wait step by step at every stage however it might within certain stage not doing anything? like add isn't using MEMORY in stage MEM .. so it's like overhead of time ... am I right? thanks alot.

 

when you say add, are you referring to ++ ?

if so... though never studied it, your need memory for it to be stored, a register to hold on to it, an addition circuit and then back to memory.

Only guessing but for it to pass thru every stage would be rather hot thus you would have to run slower or it burn.
The First stages probably use larger transistors so can run hotter though space would make it slower.

Again, never studied it though designing my own platform.

 

Something else about pip-lining , its performance should be faster than non-pip lining, lets assume that I've lw so the time in non-pip lining is smaller than the time of pip-lining. ... so how pipelining is good idea and good performance?!

 

Probably yes as get on to the next job, though possibly if it's the last stage may be quicker to perform it than to tell the system to stop the stage?

Though I'm a little confused to your stages as it's about instructions stored as a program. If an if command is successful then go on to the next line of the program.

You can't stop compare or ++ or -- etc.

 

Probably yes as get on to the next job, though possibly if it's the last stage may be quicker to perform it than to tell the system to stop the stage?

I didn't understand you, what do you mean?

 

Yes something like that, I added an edit.

Your need to study it.

So, the answer to your first question is probably not, probably different mixture of stages depending on the instruction

 

Yes something like that, I added an edit.

Your need to study it.

You didn't understand me.. I say lets assume that I have a command halt then it's latency time is 40psec, but once we use pipline its time will be 40*5(stages)=200psec and it's not faster than non-pip lining !

 

I doubt it's always stages 1-2-3-4-5. Sometimes it could be 1-3-4-5 or 3-4-5. Possibly even 3-5-2.

Processors only ever do 2 things, compare or do maths.

Compare loads one variable in a register, another in to another then compares the 2, equals, greater than or less than.
Maths is similar.

 

Nope, you're missing the concept ..

 

Well, ASM(assembly language) you load up registers, compare, add, subtract etc.
Add would not need to compare so you would not do it as a stage.
I only said possibly 3-5-2. Though the best one is 2-4-1. 3-1-4 comes in second.

 

I suggest you study MIPS design from a reputable source, some chat garbage from one to another then appears on a web page.

 

The "state machine" of a pipeline processor will certainly allow "do nothing" steps to be skipped or advanced in the pipeline. More interesting behavior happens on conditional branch instructions where the instruction after the jump might be executed before the jump happens. Optimizing the "jump slot" is something many compilers are really good at, but the resulting code can be hard to understand if you don't know where the processor "came from".

One of the humorous responses to to Dijkstra, E. Goto Statement Considered Harmful, was to propose the "ComeFrom" statement.

https://homepages.cwi.nl/~storm/teaching/reader/Dijkstra68.pdf
https://en.wikipedia.org/wiki/COMEFROM

 

The "state machine" of a pipeline processor will certainly allow "do nothing" steps to be skipped or advanced in the pipeline. More interesting behavior happens on conditional branch instructions where the instruction after the jump might be executed before the jump happens. Optimizing the "jump slot" is something many compilers are really good at, but the resulting code can be hard to understand if you don't know where the processor "came from".

One of the humorous responses to to Dijkstra, E. Goto Statement Considered Harmful, was to propose the "ComeFrom" statement.

https://homepages.cwi.nl/~storm/teaching/reader/Dijkstra68.pdf
https://en.wikipedia.org/wiki/COMEFROM

I haven't read a thing like that in 20 years, forgot they existed. Used to come across them when worked in VHS repair.

 

You didn't understand me.. I say lets assume that I have a command halt then it's latency time is 40psec, but once we use pipeline its time will be 40*5(stages)=200psec and it's not faster than non-pip lining !

Are you taking into account that the Pipeline is "PRE-FETCHED" ?
The next OP Code that is Pre-Fetched and put into the "IF" Slot of the Pipeline occurs 5 CLOCKS before it is executed.
If there were no pipeline, then the 5 steps of the microcode to process one instruction could take, up to, 5 CLOCKS.
The 5 Layer Pipeline allows the 5 steps of 5 different Instructions to be processed in PARALLEL,
so that the "1 Instruction Per Clock Cycle" goal can be achieved for many OP codes in a RISC CPU.

So, no the HALT instruction does not have a 5 clock cycle delay due to the Pipeline.

M.I.P.S. = Microprocessor without Interlocked Pipelined Stages

 

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