PIC16LF18324 uC no response from pins RA4 and RA5

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sairfan1

Joined May 24, 2012
103
I setup a project with MPLABX XC and configured project through MCC, I'm using internal OSC at 4Mhz and below code is running perfect for RA0 to RA2
but no output on RA4 and RA5, I checked Datasheet for setting up PORTA, I do not think I'm missing anythng here. RA4/5 are also used as OSC connect pins, I also checked datasheet if OSC configuration bits are needed for it but did not find anything there as well.

C:
#include "mcc_generated_files/system/system.h"

int main(void)
{
    SYSTEM_Initialize();


    PORTA = 0;
    TRISA = 0;
    ANSELA = 0;
    ANSELC = 0;       

    while(1)
    {
        __delay_ms(500);
        LATA = ~LATA;
        __delay_ms(500);
        //PORTA = 0b00110111;
        
    }   
}
here is code related to setup configuration bits
Configurations:
// Configuration bits: selected in the GUI
//CONFIG1
#pragma config FEXTOSC = HS    // FEXTOSC External Oscillator mode Selection bits->HS (crystal oscillator) above 4 MHz
#pragma config RSTOSC = HFINT1    // Power-up default value for COSC bits->HFINTOSC (1MHz)
#pragma config CLKOUTEN = OFF    // Clock Out Enable bit->CLKOUT function is disabled; I/O or oscillator function on OSC2
#pragma config CSWEN = ON    // Clock Switch Enable bit->Writing to NOSC and NDIV is allowed
#pragma config FCMEN = ON    // Fail-Safe Clock Monitor Enable->Fail-Safe Clock Monitor is enabled

//CONFIG2
#pragma config MCLRE = ON    // Master Clear Enable bit->MCLR/VPP pin function is MCLR; Weak pull-up enabled
#pragma config PWRTE = OFF    // Power-up Timer Enable bit->PWRT disabled
#pragma config WDTE = OFF    // Watchdog Timer Enable bits->WDT disabled; SWDTEN is ignored
#pragma config LPBOREN = OFF    // Low-power BOR enable bit->ULPBOR disabled
#pragma config BOREN = ON    // Brown-out Reset Enable bits->Brown-out Reset enabled, SBOREN bit ignored
#pragma config BORV = LOW    // Brown-out Reset Voltage selection bit->Brown-out voltage (Vbor) set to 2.45V
#pragma config PPS1WAY = ON    // PPSLOCK bit One-Way Set Enable bit->The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
#pragma config STVREN = ON    // Stack Overflow/Underflow Reset Enable bit->Stack Overflow or Underflow will cause a Reset
#pragma config DEBUG = OFF    // Debugger enable bit->Background debugger disabled

//CONFIG3
#pragma config WRT = OFF    // User NVM self-write protection bits->Write protection off
#pragma config LVP = ON    // Low Voltage Programming Enable bit->Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.

//CONFIG4
#pragma config CP = OFF    // User NVM Program Memory Code Protection bit->User NVM code protection disabled
#pragma config CPD = OFF    // Data NVM Memory Code Protection bit->Data NVM code protection disabled
Link to datasheet 16LF18324 PORTA at page 139 and OSC module at 76
 

fourtytwo

Joined May 16, 2022
13
//CONFIG1 #pragma config FEXTOSC = HS // FEXTOSC External Oscillator mode Selection bits->HS (crystal oscillator) above 4 MHz #pragma config RSTOSC = HFINT1 // Power-up default value for COSC bits->HFINTOSC (1MHz) #pragma config CLKOUTEN = OFF // Clock Out Enable bit->CLKOUT function is disabled; I/O or oscillator function on OSC2 #pragma config CSWEN = ON // Clock Switch Enable bit->Writing to NOSC and NDIV is allowed #pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable->Fail-Safe Clock Monitor is enabled
This has far to many silly clock modes set, no wonder RA4/5 don't work!
Try simply setting FOSC_INTOSC and nothing else.
 

BobTPH

Joined Jun 5, 2013
8,998
Yes, you are telling it you have a crystal on R4 and R5. It tries it, then the clock fail mechanism switches to the internal oscillator, but R4 and R5 are left unusable.
 
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