Hi, I have some questions regarding PCB layers.

There are two types are dielectric layers between copper layers. They are called prepreg and core materials. In a two layer board which dielectric do we have in between top and bottom copper layers, is that core or prepreg ?

I read that cores are copper clad-laminates and they are fully cured and their thickness does not change after the lamination. But prepreg are semi-cured and they used as bonding material between two core laminates given that both side of core are copper layers. After lamination the height of the prepreg change which canbe seen in attached stakup.

How the final thickness of the prepreg changes in manufacturing, some explanation please ? The core height remains the same. How about the copper height ? does it remain same in final production ?

I also don't understand how the first dielectric under the top and bottom copper layer is prepreg ? The PCB layers are staked using core with copper on each side then how we can have prepreg under the outer copper layer ?

And how the percentage of copper is changing in the inner layers and not on the outer layers ?

 

Hi,
I shall try and answer your questions within your original text:

Hi, I have some questions regarding PCB layers.

There are two types are dielectric layers between copper layers. They are called prepreg and core materials. In a two layer board which dielectric do we have in between top and bottom copper layers, is that core or prepreg ?
A double sided board is simply manufactured on a copper clad laminate, i.e - between the copper layer there is a core, fully cured, with fixed thickness.

I read that cores are copper clad-laminates and they are fully cured and their thickness does not change after the lamination. But prepreg are semi-cured and they used as bonding material between two core laminates given that both side of core are copper layers. After lamination the height of the prepreg change which canbe seen in attached stakup.

How the final thickness of the prepreg changes in manufacturing, some explanation please ? The core height remains the same. How about the copper height ? does it remain same in final production ?
Imagine the prepreg as "adhesive" that you use to attach two surfaces - it must flow to accomodate to the surface. The prepreg is only semi-cured, thus under the heating of the lamination step it flows, fills the gaps between the traces and changes a little in thickness. So - the thicker the copper - more gaps to fill
Of course, the flow is viscous and it is also limited by the reinforcement (usually by glass fabric) - thus there is a rule of thumb for the expected final thickness. The copper and the cores does not change in thicness, although the copper does become a little thinner (by microns) due to surface preparation steps.

And how the percentage of copper is changing in the inner layers and not on the outer layers ?
Each layer has its own percentage of copper, depending on your design. This information is very important to the manufacturer to calculate the expected prepreg thickness loss and to prevent warp and twist.
Thus - this information is indicated mainly on innerlayers.

 

What is it you are doing that you need this information? For 99.99% of electronics work, it is of no consequence.

 

@Ervin2022
Thank you very much for answering my questions. Most of my questions are answered. I am again very thankful to you.

I am still wondering about the percentage of copper in inner layers which is not 100 %. Can you please explain this bit further.

 

One more question. I have attached a picture of the core construction showing copper on both side of the core.

Is that true that the rough side of the copper is facing towards prepreg and the smooth side of the copper is facing core ?

Looking again at the picture attached in the first post. How do we get solder mask, copper top and then prepreg ? Should not it be solder mask, copper top, and core ? Assuming that PCB layers are stacking of multiple core with copper on each side.

 

@Ervin2022
Thank you very much for answering my questions. Most of my questions are answered. I am again very thankful to you.

I am still wondering about the percentage of copper in inner layers which is not 100 %. Can you please explain this bit further.

Hi,
100% copper means - full copper on all the surface. sInce you are designing traces, planes, vias and other elements - there is plane dielectric between them, so some of the copper must come off - thus, there will not be 100% copper on the surface.

 

One more question. I have attached a picture of the core construction showing copper on both side of the core.

Is that true that the rough side of the copper is facing towards prepreg and the smooth side of the copper is facing core ?
In general - the treated (rough) side of the copper is facing always the core, since it is part of manufacturing. What you see in this illustration as "roughness" is the copper traces etched on the core. See that they have a typical trapezoid shape and do not look like arbitrary roughness.

Looking again at the picture attached in the first post. How do we get solder mask, copper top and then prepreg ? Should not it be solder mask, copper top, and core ? Assuming that PCB layers are stacking of multiple core with copper on each side.

I am not sure that I understand your question. The soldermask comes on top of the outside copper.

 

Think about it. Why would there be solder mask on an inner layer? Do you solder on the inner layers?

 

Thanks again.
Just to be sure.

Q1: Copper layer is trapezoid having long side and short side, which side facing the core and which side facing the prepreg ?
Q2: Rough side of the copper is representing which side of the trapezoid ? which side of trapezoid is smooth ?
Q3: Copper foil with thickness 18 um or 35 um is available as stand alone item ? that can be placed as top layer having prepreg under it ?
Q4: The dielectric styles with glass content and resin for example 1080, 2116 applies only to prepreg and not to core ? Does this means that we do not need to chose the styles for core, we only chose dielectric styles with glass content and resin for prepreg ?

 

You still don’t understand what the “rough side” or the %copper you are talking about is. It is the etched copper. Some copper had been removed, so it is not smooth, and not 100% covered.

Once again, why are you concerned? Unless you are designing GHz frequency circuits, use the defaults the manufacturer uses.

 

This is a pretty standard 4 layer stack. You can specify to your hearts desire but the PCB house will need to be able to make it.



3D board

Top and bottom traces with board removed


Real board

 

The layout design engineer need to define stack-up in the design tool. The question I asked are related to defining the layers in PCB. Can someone please answer the questions asked in post # 9. I rephrase them here as well.

Q1: Copper layer is trapezoid having long side and short side, which side facing the core and which side facing the prepreg ?
Q2: Which side of the copper trapezoid is smooth ? Which side of the copper trapezoid is rough ?
Q3: The four layer stakup is
[Solder Mask Top]
[Copper Foil Top]
[Prepreg]
[Copper - Core - Copper]
[Prepreg]
[Copper Foil Bottom]
[Solder Mask Bottom]
The core is fully cured while prepreg is semi cured. The core is available in different thickness with copper in each side.
The [Copper Foil Top] or [Copper Foil Bottom] is normally 18 um or 35 um. Is it available as standalone item ? to be placed on the prepreg ? I assume they fist pick up [Copper - Core - Copper] then apply [Prepreg] on each side top and bottom and then place [Copper Foil Top] and [Copper Foil Bottom] and press all together. If yes, then copper layer is available with core in between and also as standalone item, right ?

Q4: The dielectric cloth styles with glass content and resin for example 1080, 2116 applies to both Prepreg and to Core ? This means we can also chose cloth styles for Core material as well, right ?

 

The layout design engineer need to define stack-up in the design tool.

What is the design tool?

What special considerations do you have that prevent using the defaults. No one else seems to need to do this, why do you?

I am still trying to figure out why none of us need to do any this and you do. It sounds to me like you are reading some text that bears no relation to how things are actually done.

 

What is the design tool?

What special considerations do you have that prevent using the defaults. No one else seems to need to do this, why do you?

I am still trying to figure out why none of us need to do any this and you do. It sounds to me like you are reading some text that bears no relation to how things are actually done.

It is my impression the answer to your question is “cognitive style”. I have worked with people who do excellent work but can’t tolerate not understanding a process from start to finish before beginning. You can think of it as a “quirk”.

It has advantages—and clear disadvantages. In this, just as in the TS’ previous PCB question, I think he just needs to understand what is happening to be comfortable starting.

I had a partner who, after we’d moved on, called me out of the blue…

D: I can’t use my computer.
Y: OK, what’s wrong with it, what doesn’t it do?

D: There’s nothing wrong with it—it’s just that… well… before I turn it on, it’s not doing anything but after I do, something happens and suddenly, it’s a computer. What is going on?
Y: Oh, you need to know how the boot process works.

D: I guess that’s it—I just want to understand how the inert thing suddenly can be a computer.
Y: Well, there is a lot involved, but you have actually zeroed in on one of the first problems the people engineering computers encountered: how do you make a computer “pull itself up by it’s own boot straps?”. That’s why it’s called “booting” the computer, and the first program to be run is the “bootstrap loader”.

(Overview explanation of the boot process…)

D: Thanks! Now I can use my computer.
Y: Glad I could help.

So, it is my surmise, but admittedly no more than that, the TS has a similar cognitive style and needs to feel he knows what is going on, even if he will never use the information practically. Though, to be fair, the more you know about fundamentals the more refined and effective your practical use can be—even if the connection is not immediately clear.

 

The layout design engineer need to define stack-up in the design tool. The question I asked are related to defining the layers in PCB. Can someone please answer the questions asked in post # 9. I rephrase them here as well.

Q1: Copper layer is trapezoid having long side and short side, which side facing the core and which side facing the prepreg ?
Q2: Which side of the copper trapezoid is smooth ? Which side of the copper trapezoid is rough ?
Q3: The four layer stakup is
[Solder Mask Top]
[Copper Foil Top]
[Prepreg]
[Copper - Core - Copper]
[Prepreg]
[Copper Foil Bottom]
[Solder Mask Bottom]
The core is fully cured while prepreg is semi cured. The core is available in different thickness with copper in each side.
The [Copper Foil Top] or [Copper Foil Bottom] is normally 18 um or 35 um. Is it available as standalone item ? to be placed on the prepreg ? I assume they fist pick up [Copper - Core - Copper] then apply [Prepreg] on each side top and bottom and then place [Copper Foil Top] and [Copper Foil Bottom] and press all together. If yes, then copper layer is available with core in between and also as standalone item, right ?

Q4: The dielectric cloth styles with glass content and resin for example 1080, 2116 applies to both Prepreg and to Core ? This means we can also chose cloth styles for Core material as well, right ?

https://resources.altium.com/p/pcb-core-vs-prepreg-material-what-designers-need-to-know


https://jlcpcb.com/impedance
Multilayer high precision PCB's with impedance control

 

From @nsaspook’s link:

As more designers must become intimately familiar with working at GHz frequencies, these points become quite important for properly sizing traces on these materials and avoiding complicated signal integrity problems.

I suspect the TS is not working at GHz frequencies.

 

Sorry, we are working with 10 Gbps. We are using Mentor Graphics Xpeditation.

 

Sorry, we are working with 10 Gbps. We are using Mentor Graphics Xpeditation.

You could have told us that when I asked in post #3.