Hi I'm trying to understand how it work this circuit , someone of you can explain me why the voltage characteristic is like this?
Precisely , I dont understand why at 0V I have Vout=-Vtp where Vtp is the threshold voltage of PMOS. However if you can explain me step by step how the mosfet change their state would be really helpful . Thank you.
Just assume : for example VDD=5V, VTN=0.5, VTP=-0.6

In the next picture I show the result of my simulation in LT SPICE (in which I used a MOSFET LEVEL 1 model)

 

Your LTspice circuit doesn´t match the circuit you posted before it. Correct it and things might start to work. Also it is a good habit to put dots on lines which are connected together, this circuit otherwise leaves a lot of room for interpretation.

 

Thanks for the answer, however also if not on purpose the mismatch between the two circuit is not relevant for the result of the simulation indeed both circuits generate the same plot however if this create some confusion, then refer only to the simulated circuit.

 

So first of all, you have P and N channel fets swapped. Second, the substrate really needs to be connected to GND and Vdd respectively, not to the output. See http://nptel.ac.in/courses/117103066/chap2/slides/slide32.htm and http://sub.allaboutcircuits.com/images/04143.png for reference, all N-channels need to have have substrate to ground, P-channels to Vdd.

 

So first of all, you have P and N channel fets swapped. Second, the substrate really needs to be connected to GND and Vdd respectively, not to the output. See http://nptel.ac.in/courses/117103066/chap2/slides/slide32.htm and http://sub.allaboutcircuits.com/images/04143.png for reference, all N-channels need to have have substrate to ground, P-channels to Vdd.

Thanks again for your answer , however I think you didn't read so well what I wrote and the title or I didn't explain so well mea culpa . I try to explain simply again. My purpose is to understand the circuit I drawed and precisely that one not an inverter cmos . As the title say I would like to understand that circuit which is a common drain . ( for this reason pmos and nmos are not swapped are there on purpose. Second because I want to understand precisely that circuit this means that the purpose is connected in that way on purpose . in conclusion I want to analyze the common drain drawed in the simulator and not an inverter . I hope is clear . Let me know if you have some doubt thank you

 

Ok, the title saying "CMOS inverter" got me confused.
What you have constitutes a buffer aka push-pull amplifier basically equivalent to this: http://www.learningelectronics.net/images/quiz/00968x01.png
The flat line in the middle could be called crossover distortion, and what I think is what happens in this case is that the two mosfets beign exactly identical, and with the supply voltage being very low, the mosfets are both conducting when Vin is close to Vcc/2. Try plotting both drain currents as well to see better what is going on.
Also, you can try adding some load to the output and see what happens.

 

Ok, the title saying "CMOS inverter" got me confused.
What you have constitutes a buffer aka push-pull amplifier basically equivalent to this: http://www.learningelectronics.net/images/quiz/00968x01.png
The flat line in the middle could be called crossover distortion, and what I think is what happens in this case is that the two mosfets beign exactly identical, and with the supply voltage being very low, the mosfets are both conducting when Vin is close to Vcc/2. Try plotting both drain currents as well to see better what is going on.
Also, you can try adding some load to the output and see what happens.

Thank you again for your suggestions , do you have any idea what happen for vin =0 I mean in which states are the mosfet and why?
Regard the title , if is written inverter cmos then mea culpa however I was so sure the title was : particular common drain coma. doesn't matter thanks again for the suggestions

 

Can you post your asc file?

 

That is the model level 3.

 

Hi bordodynov thanks for your helpful hint , can I ask you how can you know is level3? I mean how can I understand is level 3 ?

 

Model Level 3 takes into account the influence of the size of the transistor to the threshold voltage,
the speed limit of carriers (electrons and holes), subthreshold current(NFS and TOX), dependence of the mobility on the gate voltage(Theta). The drain current of the transistor level 3 in the formula is less than the drain current of the transistor level 1 (at (FB + 1) times). The boundary between triode and pentode regions shifted to the origin.
I am a former developer of integrated chips (CMOS, BJT). I mostly used the model of level 2 and 3 (computer calculation). Level 1 I have only used the manual calculation (approximate calculation). I was engaged in the definition of the model parameters of the experiment.

 

Model Level 3 takes into account the influence of the size of the transistor to the threshold voltage,
the speed limit of carriers (electrons and holes), subthreshold current(NFS and TOX), dependence of the mobility on the gate voltage(Theta). The drain current of the transistor level 3 in the formula is less than the drain current of the transistor level 1 (at (FB + 1) times). The boundary between triode and pentode regions shifted to the origin.
I am a former developer of integrated chips (CMOS, BJT). I mostly used the model of level 2 and 3 (computer calculation). Level 1 I have only used the manual calculation (approximate calculation). I was engaged in the definition of the model parameters of the experiment.

Thanks for your reply however I would like to know how did you understand I used a level 3 mosfet just by looking my simulation

 

I got it now. So what you meant is the model LEVEL 1 gives only an indication of what should happen although the more precise models predict a behaviour quite different is correct?

 

This is the model i used , i hope someone can help me to analyze this circuit , by describing how Vo should change by changing Vin and how the PMOS and NMOS change their state and why. I need also to find then a way to design this device. I just want point out that i have to analyze and design this circuit assuming an infinite load . Actually the output will be probably connected to the gate of another mosfet thats why i assumed infinity load. If you know some reference when all of this is described please link it here...I hope you have good day...see you soon