Hi ; may please anyone explain to me how actually devices working simultaneously in parallel? it looks for me just a weird feature that devices are working in parallel ...., I'm accepting the idea that devices working respectively !

thanks for helpers and I really struggle that thing how in parallel can devices work altogether?!

 

Hello.

Your question lacks clarity. What sort of devices are you referring to? Passives like resistors and capacitors? Active devices like transistors and ICs?

Also, “how” and “work” need to be defined.

Maybe a picture would be helpful, too, but if you can clear up the first part it might not be necessary.

 

Hello.

Your question lacks clarity. What sort of devices are you referring to? Passives like resistors and capacitors? Active devices like transistors and ICs?

Also, “how” and “work” need to be defined.

Maybe a picture would be helpful, too, but if you can clear up the first part it might not be necessary.

I relate by devices (LOGIC GATES LIKE TRANSISTORS etc) , for example on datapath of a processor, there would be many devices are working on the same stage per clock cycle , what's confused me so how they are all working together in parallel on the same time?! looks weird, maybe I'm not good enough at hardware concepts, but just want to verify how things going over working in parallel

 

Well, I think you will need to provide a schematic of an example, along with a description of what you think is happening in the schematic and which part(s) you aren’t understanding.

I can’t work out the crux of your question, perhaps someone else is understanding better, and will answer.

 

Well, I think you will need to provide a schematic of an example, along with a description of what you think is happening in the schematic and which part(s) you aren’t understanding.

I can’t work out the crux of your question, perhaps someone else is understanding better, and will answer.

lemme make it simple for you, lets assume that I have a digital circuit like this:
https://www.google.com/search?biw=1...j0i30j0i5i30.h8lZ1J4W_g0#imgrc=lnyHMYhnaiLyCM:

so in the second stage there're three gates (two AND and one XOR) , so , I'm asking how in the second stage can gates work altogether in parallel?! thanks alot.

 

so in the second stage there're three gates (two AND and one XOR) , so , I'm asking how in the second stage can gates work altogether in parallel?! thanks alot.

OK, so there is one last thing to clear up. What problem do you see that would prevent them from operating together? Why would they not work as they clearly do? What’s missing in your understanding that confuses you?

For example, are you concerned about propagation of the signals? Something else?

 

There are many architectures that exhibit various forms of parallelism.

Time slot approaches, several processes, each runs for a short time, then
passes control to next process in a round robin approach so it appears all
are running "parallel".

Truly parallel, parallel : busses, multiple memories or dual port memories,
multiple CPUs, ......like dual core, multi core devices. Several devices in
embedded marketplace offering multi core ARM solutions now.

Then in between, normal CPU and memory, but a DMA process that steals
or uses unused buss cycles to move data in and out of peripherals. Peripherals
anything from COMM to specialized ALUs. Allow CPU to continue working with
all this stuff working in background.

Lastly there is ASIC, Gate Arrays, FPGA that can create any combo of the above.


Regards, Dana.

 

The inputs to the three gates in the second stage see the same signal from the first stage. As long as the outputs of the first stage can supply the necessary voltage required by the second stage and current for the sum of the inputs current requirements, the second stage will operate.

I am going to make up some numbers here for illustration. If the first XOR gate can supply 20mA @5V, then it can drive the succeeding XOR and AND gates, if they require less than 10mA @ 5V on their inputs.

But if they require 15mA of current, they won’t work.

Most gates specifications allow them to drive many gates. It’s in their datasheet (for the life of me, I can’t remember the term)

In summary, they can work in parallel because electrically, they are within spec.

Ah! The term is fan-out

 

lemme make it simple for you, lets assume that I have a digital circuit like this:
https://www.google.com/search?biw=1...j0i30j0i5i30.h8lZ1J4W_g0#imgrc=lnyHMYhnaiLyCM:

so in the second stage there're three gates (two AND and one XOR) , so , I'm asking how in the second stage can gates work altogether in parallel?! thanks alot.

The three Input Signals start at the left side of that schematic.
The three signals propagate from the left side through each Gate, with a small delay, and finally appear as Outputs on the right side.
( Much like how three cars can drive down the highway at the same time - in parallel - and change lanes, as needed. )
Each Gate cause a very short delay, but eventually every input to every gate will stabilize and then the Outputs will stabilize.
You can manually compute the Boolean Logic ( Inputs change Outputs ) at each gate from Left => to => Right ( in this case )

In your example ( roughly speaking ) ...
a) The top-left XOR Gate and the bottom AND Gate will "parallel process & settle" first.
b) Then the middle XOR Gate and the middle AND Gate will "parallel process & settle" next = The "S - Sum" output is now known
c) Finally, the far-right OR Gate will "process & settle" = The "C - Carry" output is known.

It does take a small amount of time for the three (3) Input Signals to be processed into Output Signals, it is very fast, but it is not instantaneous.
There is a small time delay ( propagation ) between the sequential Step A and then Step B and then Step C.

In this case, there is some Parallel Processing and some Sequential Processing

 

The three Input Signals start at the left side of that schematic.
The three signals propagate from the left side through each Gate, with a small delay, and finally appear as Outputs on the right side.
( Much like how three cars can drive down the highway at the same time - in parallel - and change lanes, as needed. )
Each Gate cause a very short delay, but eventually every input to every gate will stabilize and then the Outputs will stabilize.
You can manually compute the Boolean Logic ( Inputs change Outputs ) at each gate from Left => to => Right ( in this case )

In your example ( roughly speaking ) ...
a) The top-left XOR Gate and the bottom AND Gate will "process & settle" first.
b) Then the middle XOR Gate and the middle AND Gate will "process & settle" next = The "S" output is now known
c) Finally, the far-right OR Gate will "process & settle" = "C" Cary output is known.

It does take a small amount of time for the three (3) Input Signals to be processed into Output Signals, it is very fast, but it is not instantaneous.
There is a same time delay ( propagation ) between Step A and Step B and Step C.

If this is the problem you're having with the idea, be aware the clock rate is selected so that any slew among the data lines is done before the output is read. It's part of the design.

 

OK, so there is one last thing to clear up. What problem do you see that would prevent them from operating together? Why would they not work as they clearly do? What’s missing in your understanding that confuses you?

For example, are you concerned about propagation of the signals? Something else?

ABSTRACTION "theoretical" yeah I'm not concerned about their working in parallel, but I imagine in physical way "in real life" how can they work altogether in parallel if we have propagation delay in electric between each device , I mean maybe some devices wants a lil time to respond to electricity to work, and maybe there are devices no need for respond time to work ..

exactly what you cleared above is what concerned me, so we are assume that they are ideal ?!

 

ABSTRACTION "theoretical" yeah I'm not concerned about their working in parallel, but I imagine in physical way "in real life" how can they work altogether in parallel if we have propagation delay in electric between each device , I mean maybe some devices wants a lil time to respond to electricity to work, and maybe there are devices no need for respond time to work ..

exactly what you cleared above is what concerned me, so we are assume that they are ideal ?!

No, they are not ideal, the propagation delay is figured into the design. The physical layout and the selection of clock rate are part of that. There is a time during which the output of the gates is invalid, but it will be valid when the clock causes it to be read.

 

These devices all have a operate time and propagation delay.
In a system, the clock frequency is selected to be longer than those combined times for all the gates, so that all the devices have changed state before the next clock pulse.
If you look in the device data sheet you will see that those times are generally quite short.

 

No, they are not ideal, the propagation delay is figured into the design. The physical layout and the selection of clock rate are part of that. There is a time during which the output of the gates is invalid, but it will be valid when the clock causes it to be read.

so saying : In the second stage the gates in parallel are working doesn't mean that they will work on the same time "but" they if they being executed then it might be they work in parallel and might one work before the other and vice versa, but primarily once we say "working in parallel" it imply that electricity arrived to all devices instantly .. so they can work in the same time or not in the same time, depend on relative propagation for each device .

 

so saying : In the second stage the gates in parallel are working doesn't mean that they will work on the same time "but" they if they being executed then it might be they work in parallel and might one work before the other and vice versa, but primarily once we say "working in parallel" it imply that electricity arrived to all devices instantly .. so they can work in the same time or not in the same time, depend on relative propagation for each device .

When considering the function of the circuit, it is not specified as continuous but at the rate of the clock. That is, "time" for the circuit is granular, and can't be seen as continuous in analyzing the functional aspect of it. This is why I said "work" needs to be defined. In this case it "works" when considered at the rate of the clock, and everything that happens between counts can be discarded in that analysis.

On the other hand, in designing the circuits, the realities of continuous time must be accounted for. The synchronous nature of digital circuits is very artificial. Time and space being inextricably linked, the "god's eye view" luxury of very small, linear digital circuits disappears when you crank up the clock rate or increase the distances between elements.

This effect makes distributed systems, in which the artificially imposed simultaneity can't be maintained, very hard stuff with all new methods like Lamport Clocks and eventual consistency. It is something like going from interlocking gears to slipping clutches, it requires abandoning certainly and finding ways to deal with temporality in a world more like Einstein than Newton.

However, in the simple case of logic you are presenting, it is just a matter of working out when everything has settled and ticking after that.

 

So to sum up the subject, if I've gates/devices working in parallel then I must take the max time of the operational gate over all the parallel devices?! not the minimum one because we always calculate the time we finish the stage ..

 

So to sum up the subject, if I've gates/devices working in parallel then I must take the max time of the operational gate over all the parallel devices?! not the minimum one because we always calculate the time we finish the stage ..

Yes, accounting for variations in the gates and the paths among them.