The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time.

The partial product summation + accumulation unit of above parallel mac is given below.http://i.imgur.com/Jd8WIyD.jpg (link to the image).

My problem : When I give input to multiplier as 00000101(5) and 00001000(8) what will be the values produced, that can be used as input of partial product generation + accumulation stage. What will be the values of S0,S1,S2,S3 And N0,N1,N2,N3 in the second image? The complete document is shared below.
http://www.mediafire.com/view/zoh8zuand88zkqx/05337888_2.pdf

Please share your ideas.I need to continue my project based on your replies.
Thanks.

 

Normally by modified booth algorithm partial products generated will be of length 16 bit for 8 bit multiplication operation.Here partial products are of 10 bit.How it will give final correct answer?