Hello, I have designed a two stage op amp with a phase margin of 63° ( with a compensation capacitance) which is sufficient to ensure good stability of the circuit. However, I still have a huge overshoot problem when I use it as a follower. How is it possible if my circuit is stable and how can it be avoided?

Also, when I use it in a summing circuit and apply an AC signal to the input, I get some oscillations in the output signal that I think are related to the overshoot issue.

 

Your verbal description is not much help in understanding your circuit or your problem. There is literally NO substitute for a schematic drawing complete with proper symbols and component values.

In the meantime, overshoot is characteristic of an underdamped system. In electronics this is controlled by resistance. In mechanics this would be due to a force that depends on velocity. That is a spring-mass system, without friction, will make a harmonic oscillator.

 

Are you sure about the phase margin? How did you find it?

 

Are you sure about the phase margin? How did you find it?

I used phase margin function in cadence ADE and I've also check it by plotting the open-loop gain and phase

 

I used phase margin function in cadence ADE and I've also check it by plotting the open-loop gain and phase

Post that plot.

 

Here's the open loop gain and phase of my op amp. My PM is about 55° ( and not 63° my bad)

 

That is not the Bode plot of a typical op amp.
Normally an op amp has a very high DC open-loop gain and is compensated with a single-pole rolloff starting at a low frequency, so that it is stable with feedback (see example below).
Note the constant 20dB/decade rolloff, with a constant 90° phase-shift.

 

Here's the open loop gain and phase of my op amp. My PM is about 55° ( and not 63° my bad)

Please, be exact. The PM is found from the LOOP GAIN plot. That is the complete loop including opamp and feedback function. Because - for DC - we always need negative feedback, the phase plot for the loop gain must start at -180deg (when the phase inversion at the inverting opamp input node is included).

 

Here we are 8 posts into this thread, and we still don't have a schematic. What is the part number of this alleged opamp?

 

Here we are 8 posts into this thread, and we still don't have a schematic. What is the part number of this alleged opamp?

According to the first post, the TS designed it.

 

Here we are 8 posts into this thread, and we still don't have a schematic. What is the part number of this alleged opamp?

I'm sorry I don't have the schematic right now, I only have the result plots but it is a folded cascode op amp with a class AB output stage and I have used a compensation capacitance to achieve a higher PM

 

Please, be exact. The PM is found from the LOOP GAIN plot. That is the complete loop including opamp and feedback function. Because - for DC - we always need negative feedback, the phase plot for the loop gain must start at -180deg (when the phase inversion at the inverting opamp input node is included).

I have only used the open loop plots to ensure good stability. I thought the phase margin is taken from the open loop characteristics. I haven't checked the loop gain but I will thank you.

 

According to the first post, the TS designed it.

Even more reason for a schematic if the TS is looking for help in identifying a problem and possible solutions. There are some savvy IC designers here and I would have to take a back seat to them.