Open loop closed loop logic of calculating OPAMP stability

Thread Starter

yef smith

Joined Aug 2, 2020
756
Hello, I have took just as an example the circuit below where feedback loop marked in red arrow.
i know that phase margin is calculated using this loop and when this loop disconnected.
why do we connect and disconnect the loop when calculating phase margin?
LTSPICE file is attached.
Thanks.

1705245861879.png

1705245835586.png
 

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LvW

Joined Jun 13, 2013
1,760
The phase margin is defined (and can be found) for the loop gain only. This means: We have to open the loop because we need a test signal which is injected into the loop. At the same time, the "normal" signal input must be grounded because we need the signal output at the other shore of the opening for finding the gain around the complete loop.

If you want some comments to your simulation results, you should explain which quantities the diagram shows,
 

Thread Starter

yef smith

Joined Aug 2, 2020
756
Hello LvW, can you please show me a simple pricticle example of loop phase margin stability test so I could interpret your words properly ?
Thanks
 

LvW

Joined Jun 13, 2013
1,760
Hello LvW, can you please show me a simple pricticle example of loop phase margin stability test so I could interpret your words properly ?
Thanks
There are many articles and contributions - also in this forum - regarding loop gain simulation and phase margin definition resp. determination. Perhaps you should try to spend some time for searching and reading.
 

Papabravo

Joined Feb 24, 2006
21,227
Here you go:
1705257065197.png
The required steps to get from closed loop to loop gain configuration:
  1. Ground the AC Input Stimulus
  2. Break the loop at the opamp negative input
  3. Give the two nodes unique names, e.g. "fb" and "im"
  4. Insert a 0 VDC source to close the loop again
  5. Give that voltage source an AC=1 stimulus
  6. Run the simulation
The ratio of fb/im is determined by the loop gain. Plot B(fb)/V(im). the phase margin (40° in this case) is on the phase plot above the point where the gain plot crosses the 0 dB point.

ETA: Read this thread for additional context
Op Amp Stability - How to calculate loop gain | All About Circuits
 
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Papabravo

Joined Feb 24, 2006
21,227
Okay, I'm confused.
Isn't that ratio simply the AC voltage of source V1, which would be a ratio of 1?
There is also some debate about the efficacy of this method close to the 0 dB crossover. Your question has piqued my interest in looking further.
ETA: It appears that there are multiple methods which go by the names Tian, Middlebrook, and Big Inductor. The Tian and Middlebrook methods are illustrated in the Examples folder of LTspiceXVII as LoopGain.asc and LoopGain2.asc. The big inductor method was described (I think) in Basso, Christophe, Switch Mode Power Supplies, 2014

Here is a thread that discusses the differences.
Calculating open loop gain using LTSpice | diyAudio

I'm not sure if those examples were in the LTspiceIV distribution.
 

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Papabravo

Joined Feb 24, 2006
21,227
Well, that doesn't really make sense to me, but apparently it works.
I understand your incredulity. One of the alternate suggestions for allowing the potential on both sides of the thing that "breaks the loop" to be fixed at DC but variable in AC is a bi-directional(?) filter with a corner at 1E-3 radians per second; and it might be related to what the referenced discussion meant by the big inductor (1kH) along with a big capacitor (1kF). That is the only thing that comes close to sounding like a reasonable explanation of what is required.
 

Thread Starter

yef smith

Joined Aug 2, 2020
756
Hello, i intend to plug a signal generator in the input and view the output on osciloscope.
I will sweep the frequency and get a body plot.
You said i need to open the loop to see the stability,but in real life i cant.
Is there a way suitedto analyse real work SCOPE body plot?
Thanks.
 

LvW

Joined Jun 13, 2013
1,760
Well, that doesn't really make sense to me, but apparently it works.
Yes, of course it works.
It is nothing else than a shorted method as proposed by Middlebrook in his phantastic paper.
However, it must be noted that this short and simple method works only in case that at the breaking point there will be no remarkable change of the loading conditions (compared with the closed-loop condition).
Because the test ac source is located BETWEEN both nodes at the opening there will be no change of the DC operating point.

That means: In case of opamps we have two simple alternatives for breaking the loop:
* Opamp output (very small output resistance) , or
* Opamp input (very high input resistance).

In case such a point cannot be found, Middlebrook explains that - in addition to the test voltage - a test current source must also be used.
Then, the loop gain results from a combination between both simulations using a specific formula.
 

Thread Starter

yef smith

Joined Aug 2, 2020
756
Hello LVW, So when i am in the lab an i cant open the loop like in a simulation.
i only have closed loop gain bode plot.
what method you reccomend for real lab bode plot?
Thanks.
 

LvW

Joined Jun 13, 2013
1,760
Hello LVW, So when i am in the lab an i cant open the loop like in a simulation.
i only have closed loop gain bode plot.
what method you reccomend for real lab bode plot?
Thanks.
Of course, you can measure the closed-loop response (if you like) - however, the phase margin can be determined for open-loop measurements resp. simulation only.
 

Thread Starter

yef smith

Joined Aug 2, 2020
756
Hello LvW,simulations doesnt take into account parasitics.
for example input parasitic capacitance in opamp intreduces anothe pole and ruins stability.
Sorry for not understanding and answer, is there purely lab measuremnt methos tho get loop gain stability?
Thanks.
 

LvW

Joined Jun 13, 2013
1,760
Hello LvW,simulations doesnt take into account parasitics.
for example input parasitic capacitance in opamp intreduces anothe pole and ruins stability.
Sorry for not understanding and answer, is there purely lab measuremnt methos tho get loop gain stability?
Thanks.
* When you want to include parasitics during simulation - who is stopping you from using a small capacitor at one of the nodes?
* When the closed-loop circuit works (amplifies) as desired, it will be stable.
However, the degree of stability (phase margin) can only be estimated by analyzig the step response. An exact analysis requires to make a Bode plot for the loop gain.
 

Thread Starter

yef smith

Joined Aug 2, 2020
756
Hello LvW,i want to create a picture as close as possible to reality.I dont know how in the lab to know the parasitic capacitances i have in my OPAMP pcb.
Could you suggest a way to estimate parasitic capacitances?
 

LvW

Joined Jun 13, 2013
1,760
Okay, I'm confused.
Isn't that ratio simply the AC voltage of source V1, which would be a ratio of 1?
My short explanation:
It is the DIFFERENCE between both voltages (left and right from the ac source) which equals the value of the ac source.
However, the RATIO can assume other values (Examples for Vac=1V: 1.01/0.1=11 and 100/99=1.010101)
 
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Thread Starter

yef smith

Joined Aug 2, 2020
756
Hello :) wrong thread.
but i'll be happy if you could help me with the real life stability method as i explained in post 18
 
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