Open Drain or Open Collector Configuration

Thread Starter

Abhinavrajan

Joined Aug 7, 2016
83
I am finding very difficult and confusing to understand the concept of The Open Dain or Open collector configuration.
Can someone explain in clear and simple English with an example.
 

hp1729

Joined Nov 23, 2015
2,304
I am finding very difficult and confusing to understand the concept of The Open Dain or Open collector configuration.
Can someone explain in clear and simple English with an example.
TTL logic ... The output can only be pulled low. Some external circuit is assumed that will pull the output high. This allows for outputs to be tied to non-logic levels......., higher voltages or higher currents. It also allows more than one output to be tied together.
CMOS Logic ... the open drain can be either the low side (N-MOS, active sink only) or an open drain on the high side (P-MOS, active source only). Advantages are the same as TTL.

Would pictures help?
 

hp1729

Joined Nov 23, 2015
2,304
Design 813 7405 06 07 16 17.PNG

Design 814 CMOS open drain.PNG
TTL logic ... The output can only be pulled low. Some external circuit is assumed that will pull the output high. This allows for outputs to be tied to non-logic levels......., higher voltages or higher currents. It also allows more than one output to be tied together.
CMOS Logic ... the open drain can be either the low side (N-MOS, active sink only) or an open drain on the high side (P-MOS, active source only). Advantages are the same as TTL.

Would pictures help?
Mod edit: shown images full size
 
Last edited by a moderator:

Papabravo

Joined Feb 24, 2006
14,702
On the die of the integrated circuit you fabricate a transistor, BJT or FET, with only two of its nodes connected. These nodes would be the base and emitter for a Bipolar Junction Transistor (BJT) or the gate and the source for Field Effect Transistor(FET). Why would you do this you ask? Two reasons:
  1. So the collector or drain can be connected via external circuitry, usually a single resistor, to an arbitrary power source to perform level shifting.
  2. So multiple outputs can be connected together to perform an additional logic function. In this case an AND function.
 
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