Do some research on NMOS or PMOS designs from the 70's.
Ahahah Friday nights ahahah been there done that ahah.We guessed!
The constant current load circuit you have will be about 25% efficient.
You can get to about 50% and remain in class A by using semiconductor versions of White cathode follower and SRPP valve circuits.
You can get to 78% using class B (just a bit less for class AB, which is Siliconix Autobias etc.)
Class D will take you into the >90% region.
I remember taking a lecture course on amorphous silicon back in my 3rd year at university back in 1986 - I remember it being scheduled for 9am on Saturdays.
What I don't remember from it (maybe due to what I was doing on Friday nights) is whether the FETs were enhancement or depletion or whether you could make both, and whether you could construct P-channel devices.
Due to the nature of the IGZO transistors I think I can't make depletion ones. :s

