Only NMOS output stages - [scientific investigation]

Thread Starter

dumbinvestor

Joined Feb 17, 2020
27
Do some research on NMOS or PMOS designs from the 70's.
We guessed!
The constant current load circuit you have will be about 25% efficient.
You can get to about 50% and remain in class A by using semiconductor versions of White cathode follower and SRPP valve circuits.
You can get to 78% using class B (just a bit less for class AB, which is Siliconix Autobias etc.)
Class D will take you into the >90% region.

I remember taking a lecture course on amorphous silicon back in my 3rd year at university back in 1986 - I remember it being scheduled for 9am on Saturdays.
What I don't remember from it (maybe due to what I was doing on Friday nights) is whether the FETs were enhancement or depletion or whether you could make both, and whether you could construct P-channel devices.
Ahahah Friday nights ahahah been there done that ahah.
Due to the nature of the IGZO transistors I think I can't make depletion ones. :s
 

Ian0

Joined Aug 7, 2020
13,158
Well this just made my day ahah Thanks you very much!!!
If you can make depletion-mode devices, then look at all the possible valve circuits - everything is N-channel because you can't make P-channel valves!
http://www.valvewizard.co.uk/SRPP_Blencowe.pdf
https://www.tubecad.com/2019/04/blog0462.htm
In both cases, the circuit can be made with depletion FETs, but it is probably more efficient if the upper device is depletion and the lower device is enhancement.
 

Thread Starter

dumbinvestor

Joined Feb 17, 2020
27
If you can make depletion-mode devices, then look at all the possible valve circuits - everything is N-channel because you can't make P-channel valves!
http://www.valvewizard.co.uk/SRPP_Blencowe.pdf
https://www.tubecad.com/2019/04/blog0462.htm
In both cases, the circuit can be made with depletion FETs, but it is probably more efficient if the upper device is depletion and the lower device is enhancement.
Sure!! I'll check everything you guys send me here. You have already been more helpful than my advisor.
 

Thread Starter

dumbinvestor

Joined Feb 17, 2020
27
As a circuit designer should I be worried about process variability in transistor characteristic curves in order to develop the circuit? I mean, I would like to see this work but from my initial lab data I can see a lot of variation in Vt values and ION currents.
 

Ian0

Joined Aug 7, 2020
13,158
I design circuits so that they work perfectly with devices that have minimum, typical or maximum specs.
Agreed - but it's taken me many years to design an audio power amplifier design that doesn't need a bias adjust preset (and my circuit only works with complementary output stages)
If you've only got N-channel, then there's the Siliconix "autobias" that was mentioned previously, but it's not exactly in the -100dB distortion category.
 

Thread Starter

dumbinvestor

Joined Feb 17, 2020
27
Agreed - but it's taken me many years to design an audio power amplifier design that doesn't need a bias adjust preset (and my circuit only works with complementary output stages)
If you've only got N-channel, then there's the Siliconix "autobias" that was mentioned previously, but it's not exactly in the -100dB distortion category.
Thank you once again for taking the time to help me
 
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