Hi,
i try to understand the following circuit. Especcially transistors circuits. I have a question.
When the output of comeprator U1 is high. the base voltage of transistor Q1 is also getting high, which leads that V4 can flow to ground via Q1.
I had a discussion with a friend about this circuit and he said that the VCE can't be 10mV. That in saturation mode de VCE must be higher. When i look in the datasheet it is saying that the VCE(sat) is typical 90mV and maximum 200mV. So why is the LTSPICE value 10mV? I used the official spice model?
hopefully someone can clear this up for me
thanks in advance!
i try to understand the following circuit. Especcially transistors circuits. I have a question.
When the output of comeprator U1 is high. the base voltage of transistor Q1 is also getting high, which leads that V4 can flow to ground via Q1.
I had a discussion with a friend about this circuit and he said that the VCE can't be 10mV. That in saturation mode de VCE must be higher. When i look in the datasheet it is saying that the VCE(sat) is typical 90mV and maximum 200mV. So why is the LTSPICE value 10mV? I used the official spice model?
hopefully someone can clear this up for me
thanks in advance!
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