In the following circuit fashion i need to insert capacitors in the non overlapping circuit to reduce the glitches so how do i calculate the caps value

 

You add a resistor at the output of each gate before the capacitor.
The RC value is then determined by how much non-overlap you need, which you have not given.

 

how do i calculate the desired delay in the step wave form shown below to reduce the glitches (known values resistancw unknown values cap and time)

 

What is that a plot of?