Non overlapping clock genrator

crutschow

Joined Mar 14, 2008
34,452
You add a resistor at the output of each gate before the capacitor.
The RC value is then determined by how much non-overlap you need, which you have not given.
 

Thread Starter

Anonym0us guy

Joined Feb 19, 2024
2
how do i calculate the desired delay in the step wave form shown below to reduce the glitches (known values resistancw unknown values cap and time)dac_ideal .jpg
 
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