hi friends

i am having problem in finding the noise margin for ttl gates
when a ttl logic circuit is given

if any one know abt that plz help me

waiting for ur reply

 

it s pretty easy to calculate if u have the logic levels of both the input and the output of the ic!!

just subtract the levels considered as high and also the levels considered as low!!!

for example if for input u have from 0V to 1.5V considered as low and on the output the low level rang is from 0 to 0.9V then you have a nois margin of 1.5 - 0.9V i.e a noise margin of 0.6!!

hope you understood what i was trying to explain!!
btw if u ve got the logic levels given it would really help out if u post those here as well!!

bye bye for now!