Hi,
I am reading Digital Integrated Circuits by Rabaey. As per book - cmos has high input impedance and that helps in cmos to get high noise margin.
I understand why cmos has high input impedance and I understand what is noise margin but I am not able to understand how does having high input impedance help in high noise margin.
Please can one you help me understand this.
Regards,
Twain

 

I don't understand either. CMOS logic has a high digital noise margin because the logic threshold voltage is near 1/2 the supply voltage. That has nothing to do with a high input impedance, so I think that book is incorrect if that is what it states.