Hi,

I made a bidirectional NMOS level shifter translating the signal between 1.8V and 3.3V. The circuit works well when using R1=1k to get a satisfactory rise time:

A side effect of using R1=1k is that the signal now shifts between 200mV and 3.3V instead of 0 and 3.3V. This effect I am able to simulate by adding 100R/100p parasitic properties to the pulse generator. The 1M (R3) and 100p (C1) is to simulate the load.

When testing this circuit and observing with an oscilloscope, there is an effect I don't understand. The slew rate, when going from low to high, is first very fast, then it slows down. This is not an issue for the overall performance, but I am curious why the slope looks like this:




The breaking point where the slew rate decreases is at about 1.37V.

This is probably caused by the NMOS transistor's nature, but I don't know exactly what is happening.
Anyone who can explain this rising curve?

 

It is called Miller capacitance. The switching of a MOSFET requires a circuit that will use current, not voltage, to supply or remove charge from the gate. The amount of charge to be supplied is given in the datasheet. The process happens in 3 steps. There is an initial rise, a plateau, and then another rise to the final value. Read more about it in the following article:

Miller effect - Wikipedia

 

It is called Miller capacitance. The switching of a MOSFET requires a circuit that will use current, not voltage, to supply or remove charge from the gate. The amount of charge to be supplied is given in the datasheet. The process happens in 3 steps. There is an initial rise, a plateau, and then another rise to the final value. Read more about in the following article:

Miller effect - Wikipedia

Great! Thanks!