Hello,I have following problem and I wish,if possible, your help to resolve it.

Size the following circuit so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs. (VDD = 2.5V) Assume A, B and their complements are available as inputs.


Other data available for NMOS are following
Vt=0.43(V),Vdsat=0.63(V),k'=115x10^-6 (A/V^2),lambda=0.06(v^-1)

I think that I should size W/L for NMOS transistors,can you give me any advice to start ? Moreover,what is the double inverter funcion in this circuit?

 

For first step I computed the current of charge/discharge on 100fF capacitor,Ic=C*(dv/dt) with dv/dt=(vdd/2)/T.....is it correct for firts approach?

 

any help??