@WBhan, my if statements are completely wrong, I just wrote that off the top of my head, sorry about that!
@AKthank you so much for providing the options of polling and interrupts, those seem ideal.

Sorry if I'm asking for too much, but would you be able to give me a quick explanation of how you determined the 100ns quantization error? From what I understand, quantification error is usually used when dealing with ADCs.

I understand the other part about having to sample the units 20Million/sec to get the output edge within 10% of the input edge (0.10*20Million/sec = 2Mill/sec)

 

Are the steering inputs async with respect to the data stream being routed ?
Are the 3 steering inputs asynch to each other ?

In the PSOC case posted in post # 2 that solution is a gate level solution,
so very fast. But do you want the serial stream to be synchronous to the
routing control inputs ? Seems like you would. That you would not want
the serial stream bit timing to be altered by the control inputs asynchronously
changing.

http://www2.comp.polyu.edu.hk/~comp2322/Bit and Frame Synchronization Techiques.pdf

In that case PSOC can easily resynch the stream using additional onboard
resources.

Regards, Dana.

 

So I completely disregarded a key piece of information: the inputs are synchronized as they are coming from another MCU. Does this change the game in making an MCU viable?

 

Not substantively, just insures synch is already done so stream being
routed no bits will be truncated in the stream.

So I would guess you are in low uS range to do this via code, and << 100 nS
with LUT or other gate level logic.

Regards, Dana.

 

Here is the LUT coded to handle the output enables -




Looks like delay is < 20 nS to output route change. Done with
a part $ 1.55 at single unit pricing. Wasting ~ 95% of the other
resources on the chip.

I think this can be done in a much less cost part w/o LUT by making
the LUT out of onboard gates, just not enough time to go thru it at the
moment.


Regards, Dana.

 

Thank you very much Dana! I will look into this.

 

Since you are learning, I strongly suggest you carry on to work out a design entirely with gates, and perhaps another using multiplexes or decoders (in some CMOS families there are parts that can be used either as a multiplexer or a decoder, with the signal passed by "analog switches"). This will help you develop some sense of the tradeoffs between using "random logic" and LSI (PSOC or FPGA) solutions. Sometimes the random logic solution is a good way to go because it actually turns out to be fairly simple and the parts can be very inexpensive - or a little more expensive and extremely fast. Sometimes the LSI solution makes sense because it reduces parts count and board space, though at higher parts cost and with the added burden of needing to program the parts. If you press on with your microcontroller solution, you will gain some valuable "hardware-software tradeoff" experience.

Good electronics design almost always involves making compromises one way or another. And design is always a matter of knowing what is "out there" that could be applied to your problem.

 

Yes I am actually building this right now. Thank you all for your inputs!

 

A quad AND gate costs what, 20 cents? The problem is the compiler - it is expensive and painfully slow to do anyth - wait a minute, there is no compiler.

I'd like to stick to discrete/specialized logic aka no mcu.

Then why keep asking about one?

ak

 

For learning purposes

 

For learning purposes you can use PSOC Creator to just drag and drop gates
with GUI tool, then drag and drop pins to connect them to outside world, and of
course a simple wiring tool to route them both internally and externally.

Its a great way to learn logic without having to create wiring messes on a breadboard.

Then bit at a time move on to the other 95% of its capability. You need a 32 bit counter,
but exhausted at the idea of building it out of gates and flops and 10 GIGA wires,
drag and drop that......its all good. Progress is a wonderful thing. I know trying to
build music synthesizers in the 70's out of MSI logic, will never go back to that.

Tool is free, including the compiler. For this type of work you do not care
or get involved with the compiler, you just hit the build button and the
tool generates all the internal switch matrix routing and other chip background
task like telling chip what Vdd its going to use, 3.3 or 5, tool does it all and
programs part.


Regards. Dana.