Need VHDL code help! 4 bit, serial in shift right register

Thread Starter


Joined May 2, 2018
I don't know anything about VHDL coding and I'm having a hard time finding material to learn about the coding I need. I need to add a slide switch as the input for "ser_data" and momentary switch for the input of "n_cp". But I don't know where it goes in the code and I also don't know what terms need to be used to make them inputs.



Joined Aug 24, 2010
You associate FPGA I/O to HDL nets in another file that is part of your project. For Xilinx development using the ISE software, that file is called the "UCF" file. Google it. In Xilinx Vivado they changed the format and extension of that file (it is more of a pain in the ass now, IMO). If this is for Altera, I don't know, but I'm sure it is similar.

Also, using a push-button for a clock is going to give you fits if the button is not hardware debounced (since I don't see any HDL debounce in that screen shot).