N phase buck controller logic

Thread Starter

Kevin Hall 1

Joined Jul 15, 2018
9
Hi! I've been working on a control topology for an N phase buck converter. I'm trying to keep component count as low as possible per phase, as well as minimize circuit traces with the hope of being able to copy and paste my phase circuit to go from 1 phase to 2 or 3 or thirteen. I think I've come up with a good control topology. Below is a circuit simulator that demonstrates it's function. If you want to watch it go, click run, then click the square wave button to activate the clock signal. Zoom out until you can see all six paralell channels. At the bottom is a [0] in a box that you can change to a 1. This represents the signal from the comparator that constantly checks if the current output is below the reference. 1 tells the circuit that it should be starting phases and not shutting them down. I'll call this input TurnOn

N phase voltage controller set up with 6 phases

The circuit takes 2 inputs, the clock input, and the ON input. The clock goes into a frequency divider to produce a dual clock signal. The reduced frequency clock sends pulses to the D flip flop array, which has 1 d flip flop, 1 inverter and 1 input of a multi input or gate. When a clock pulse is received, if none of the flip flops are high, the first one goes high. Otherwise whichever flip flop is currently high goes low and the one below it goes high. In this way the clock frequency is divided again into asynchronous pulses on N channels. These outputs are fed into the logic bank to the right, which controls each output. Each phase's logic bank is identical, requires 3 and gates, 2 or gates and 1 A<=B gate and an additional D flip flop,so 2 flip flops and 6 gates per phase so far. Because the frequency is an unknown, rather than converting the asynchronous on signals (which have a rather long 1/N duty cycle to pulses of unknown duration, I used a latching enable mechanism to ensure each phase turns on only once per ON signal

When a phase receives it's asynchronous clock signal, if it is enabled, it turns on and latches ON until it's enable goes low.
A phase is disabled if the phase above it receives it's ON signal. This ensures that the system never has more than n-1 channels simultaneously turned on, without preventing new phases from turning ON at the appropriate times. The remainder of the enable logic is a latching enable described by the following:
(Not(CurrentlyOn OR Receiving Pulse) OR (Already Enabled)) AND (TurnON OR ChannelAboveOutput)
I'll break this down to parts I guess.
If the phase is not currently on or receiving an on pulse, and either the channel above is on or the TurnON signal is being received, the enable goes high and stays high(latches) until both the phase above it is turned off and the TurnON signal goes low.
The first part ensures that the enable lasts for only one pulse. The enable cannot reset until the channel both turns off and it is no longer receiving it's own ON signal. "Or Already Enabled" causes the enable signal to latch when it becomes reset in this way. "
"And(TurnON OR ChannelAboveOutput)" ensures that the enable mechanism only maintains enabled state if either the TurnON signal is high, or the output above is ON.
Having an output remain enabled if the line above it is turned on ensures that the outputs always turn off one at a time, and the first one to turn off is always the first one that turned on. The D flip flop In the ChannelAboveOutput feedback line updates on base clock ticks. As a result of these factors, outputs can turn off one at a time, one per base clock tick.
The relationship between the base clock ticks and the frequency divider determines the PWM resolution of the system and the effective frequency on each channel.
Looking at the example above, I'm using the second step of the frequency divider, so a frequency of the base clock/4 is going into the asynchronous pulse splitter. The pulse splitter splits this frequency equally into the 6 channels(in this example), giving each channel an effective frequency of 1/24th the base clock signal, giving each channel a PWM resolution of 1/24 or about 4%. Using the second from bottom rung of the frequency divider would be more realistic, giving 1/(2^5*6) or 1/192 PWM resolution.

Ok, so assuming the mosfets, mosfet drivers and inductors chosen give you an ideal operating frequency of 100kHz per channel, and you wanted to use a 5 stage frequency divider for 1/192 resolution, you would want a base clock speed of 19.2MHz.

One advantage I see for this design would be for flashlight drivers. In many cases, current drivers are just stacks of 7135 linear current regulators and boards are discs to fit in the handle of the flashlight. When a low mode (brightness below the LED's turn on voltage) is required, many of these drivers actually pulse 7135s, basically receiving no benefit from the PWM and little benefit from the microcontroller.
Some of the reasons 7135s are currently used are that LEDS benefit in efficiency from a linear voltage input, meaning a steady 3.3v will run an led more efficiently than 5v pulsed to an effective 3.3v. Having a linear voltage output requires linear regulation or pulse modulation and inductors, which for a single channel at high currents can get pretty big.
A design like this, using a stack of discs, putting one phase circuit and mosfet on each side of a disc(if possible), complete with microcontroller current and mode control (which is currently included in flashlight drivers), I think might be several times as bulky in number of discs in the flashlight body, but could potentially be so much more efficient, still scalable, and be worth it. In many flashlights there is space to be used up taken by the spring, and an 18650 body could use an 18500 or 18350 battery for a good enough reason (similar battery life with the flashlight heating up less)
Given that a flashlight body has a fixed heat sinking ability, the benefits of not burning off the excess voltage as heat could be quite nice.

Another use I have planned is RGB LED supplies and drivers. Because a different voltage is needed for each color of LED, and regulation has to maintain voltage with rapid load and supply voltage changes at 200 to 600hz.

I'm pretty sure that this would also be good as a DC motor controller/driver, because at least with larger motors I'm more familiar with, it can be advantageous to be able to control both effective PWM and real voltage for startup induction and or torque situations.

At any rate, this driver logic is just part of a larger project and I thought it might be smart to be a bit more specific and coherent with my posts, as I tend to ramble. I'm working on relearning boolean algebra, but I haven't used it in about 15 years so it will be a while before I'm up to speed again. I've tried as hard as I can to reduce the number of gates per channel but I think I've taken it as far as I can at my current skill level. I tried using boolean algebra to figure it out but got stuck because I don't properly understand and know how to write the recursive relationship caused by the feedback on a latch. I'm also considering modifying it a bit to allow infinite PWM resolution by allowing the top channel to turn off immediately, but still only one phase off per clock cycle. Come to think of it, that's probably what it's doing right now. My intent in using the base clock cycle this way is that if I can control and limit the rate at which phases shut down, in a load situation where multiple of the total phases are conducting at once, I don't want a full shutdown of all phases the instant the reference voltage is reached, especially in a random load scenario where the load or reference voltage may spike at any moment. I also don't want to mess up the balance of load on the physical components by having a phase miss its turn or not come on. Phases can still turn off 192 times as fast (or as fast as you choose limited by propagation rate if I test it and this turns out to be too fast) as they can turn on, and in a no-or-low-load scenario where they were turning on anyway, but only one was running at a time, they are still able to turn off almost immediately after turning on to avoid building up voltage.

Finally, with the logic simulator above, By flipping the TurnON control input at the wrong time, I'm sometimes able to lock up the simulation. Because the whole simulation stops. I think the computer is just unable to resolve the completed logic state and go on with the next frame. If this is the case, I'm fairly certain this wouldn't happen in real life, the circuit would resolve itself, possibly incorrectly, but It is easy to replicate, and it is flashing the output and stops as soon as the TurnOn signal goes back below 0

Any input or help you can offer is very welcome.
 

danadak

Joined Mar 10, 2018
4,057
Possibly a PSOC using either schematic capture or Verilog.
Would give a lot of analog stuff as well. Possibly centered
around the dual PWM module with dead time capability.

Start with "PSOC Creator 101" video series on their web site or
on youtube.

I would advise the $10 board.

http://www.cypress.com/documentatio...oc-5lp-prototyping-kit-onboard-programmer-and

Or of course a small FPGA another approach, that of course would be sans analog.


Regards, Dana.
 

Thread Starter

Kevin Hall 1

Joined Jul 15, 2018
9
Thanks you for the microcontroller resources! I spent a lot of my childhood and young adult life programming, and I definitely want to pick a microcontroller family to add to my repertoire, but I have to admit I'm not ready for it yet. I want to keep developing my understanding of electronic logic before I add such a "one hammer fits all" tool to my bag. In truth, part of the point of my current project is to take some of the processing load off of a microcontroller and decrease the dependency on microcontroller timing for the quality of the result. The second phase of this project will be a PWM control module that accepts either a hard PWM signal or an analog 0-Vcc (0-100% duty cycle). This way the microcontroller needs only provide either 2 reference voltages (one to control the voltage and one to control the PWM) or one reference voltage and it's own arbitrary PWM signal. This should hopefully make it easier for a microcontroller of a given processing power to actively control a large number of, for example RGB modules, and from what I understand reading from people who are doing arduino or raspberry or pic projects, some of the microcontroller families handle timing, threading and interrupts in a way that makes them not function well in things like a high frequency regulator. I'm hoping that because this circuit is not timing dependent that way (biggest timing problem I see is that the propagation delay of the chain of 4 gates adds up and will limit the maximum frequency, just hopefully less than it is limited by the mosfet switching speed) it will be useful to people who are using these types of controllers for their projects, and judging by the components I've been looking at, it should function anywhere from 2v to 5v logic.
Alas, I'm similarly not ready for FPGAs yet, but could you give me a brief idea of what they're typically used for? I'm kind of getting the impression that I could have all of the logic gates on one chip, but the pictures are of rather large chips. My current circuit requires about 20mm by 10mm space on one side of the board per channel, not including mosfet driver, frequency divider and clock generator (the frequency divider and clock generator go on a separate 20mmx20mm board so that one clock signal can be used to time a large number of modules.)
I would be more ready to pursue MCs and FPGAs if I'd finished engineering, but I am an electrician now and have a lot to learn about these small signal circuits. I'll be reading the transistor related docs you posted in the brake light article as well, although my knowledge of larger electrical tells me that he shouldn't be using a mechanical relay to switch a 2.4A load 8 times a second, even intermittently, but the relay is described as "beefcake" so it might just be fine =).
 

danadak

Joined Mar 10, 2018
4,057
Alas, I'm similarly not ready for FPGAs yet, but could you give me a brief idea of what they're typically used for?
Basically wherever logic is needed. And where control over routing is
needed. They range from simple gate level to parts with ARM and DSP
cores in addition to the logic fabric.

Small parts -

https://tinyfpga.com/

https://www.altera.com/products/fpga/max-series/max-10/overview.html

https://www.altera.com/content/dam/...S/pdfs/literature/pt/max-10-product-table.pdf


The PSOC can also be used as a small FPGA. Using schematic capture and/or Verilog.

Regards, Dana.
 
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