I have noticed that the pinouts on N channel JFETs are not always the same, even if they are the same number:

J113 from Onsemi, goes DSG



J113 from InterFET goes GDS

And if you look on Component Search for the InterFET model, it's different still: SDG


I'm super confused, why isn't all this standardized for a particular package?

 

As the datasheet says: "Source and Drain are Interchangeable". This is the norm for JFETS as I know them.
Only the gate is the one to really keep an eye on. Interfet is bottom view.

 

Ahhh. I didn't know the S and D are interchangeable.

 

They are the same. Some are viewed from the pins and some from above.

 

For some dumb reason, several semi vendors still show a TO92 pin out from the BOTTOM VIEW, which may have been a thing when these devices were hand soldered, but cause a lot of confusion when using any CAD board layout package, which shows the board from the TOP VIEW.
Mind you, everything else is always shown as TOP VIEW. Even the same device in another package.