multiplexer verilog code

Discussion in 'General Electronics Chat' started by vead, Aug 2, 2014.

Nov 24, 2011
712
11
multiplexer

 module full (sel, i1, i2, i3, i4, o1); input [1:0] sel; input [1:0] i1, i2, i3, i4; output [1:0] o1; reg [1:0] o1; always @(sel or i1 or i2 or i3 or i4) begin case (sel) 2'b00: o1 = i1; 2'b01: o1 = i2; 2'b10: o1 = i3; 2'b11: o1 = i4; endcase end endmodule

 case (sel) 2'b00: o1 = i1; 2'b01: o1 = i2; 2'b10: o1 = i3; 2'b11: o1 = i4; endcase end [/FONT] [/FONT]

what is meaning of this table
I think if we put value of i1 then we will get output but what is 2'b00

Jul 27, 2014
189
10
Looks like a crock of s*it to me mate.

3. gagwd New Member

Aug 2, 2014
6
1
Where did this code come from?
It needs some help.
However in the case statement the 2'b00 is or is supposed to be the case match of the first condition. sel is being used to match with one of the 2'xx values and on a match, and there must be one since all possibilities are covered, the statement after the colon is executed.

Nov 24, 2011
712
11
look another example
multiplexer 2 to 1
 s d1 d0 q 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1
verilog code
Code ( (Unknown Language)):
1. module ( s,d1, d0,q)
2.  input s, d1, d0;
3.  output q; reg q;
4.  always @( s or d0, d1);
5.  begin
6.  case (s)
7. 1'b0 : q= d0;
8. 1'b1 : q= d1;
9.  end case
10.  end
11.  endmodule
I tried to understand in this way

1'b0 : q= d0

 q d0 s 0 0 0 1 1 0 0 0 0 1 1 0
I don't know its correct or wrong

Last edited: Aug 3, 2014