multiplexer verilog code

Thread Starter

vead

Joined Nov 24, 2011
629
multiplexer


module full (sel, i1, i2, i3, i4, o1); input [1:0] sel; input [1:0] i1, i2, i3, i4; output [1:0] o1; reg [1:0] o1; always @(sel or i1 or i2 or i3 or i4) begin case (sel) 2'b00: o1 = i1; 2'b01: o1 = i2; 2'b10: o1 = i3; 2'b11: o1 = i4; endcase end endmodule
case (sel) 2'b00: o1 = i1; 2'b01: o1 = i2; 2'b10: o1 = i3; 2'b11: o1 = i4; endcase end

what is meaning of this table
I think if we put value of i1 then we will get output but what is 2'b00
 

gagwd

Joined Aug 2, 2014
6
Where did this code come from?
It needs some help.
However in the case statement the 2'b00 is or is supposed to be the case match of the first condition. sel is being used to match with one of the 2'xx values and on a match, and there must be one since all possibilities are covered, the statement after the colon is executed.
 
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