So I'm in a computer architecture class, and I'm stuck on a question about Multiplexers:

A device accepts natural binary numbers (N3N2N1N0) in the range 0000 to 1111 that represent 0 to 15. The output of the circuit, PRIME, is true(1) if the input to the circuit represents a prime number and is false (0) otherwise. A prime number is an integer that is greater than 1 and is divisible only by itself and 1. Zero and one are not prime numbers.

And this is what I need to do:

Design a circuit for this device using:
-An appropriately sized decoder
-An appropriately sized MUX where N1 is used to drive the inputs
to the MUX. Draw the MUX as a block diagram.

How exactly would I go about doing this? I'm not even sure where to start, tbh.

 

First thing to do would be to create a truth table to determine what the output of the device should be for every possible combination of inputs to the device.

So, for your circuit, you will have something like:

| Inputs | Output decimal | N3N2N1N0 | Y
0|0000|
1|0001|
2|0010|
3|0011|
4|0100|
5|0101|
6|0110|
7|0111|
8|1000|
9|1001|
10|1010|
11|1011|
12|1100|
13|1101|
14|1110|
15|1111|

*if you want to input information into the table, click "Quote" and copy the corresponding code, filling in data where appropriate...

 

So I'm in a computer architecture class, and I'm stuck on a question about Multiplexers:

A device accepts natural binary numbers (N3N2N1N0) in the range 0000 to 1111 that represent 0 to 15. The output of the circuit, PRIME, is true(1) if the input to the circuit represents a prime number and is false (0) otherwise. A prime number is an integer that is greater than 1 and is divisible only by itself and 1. Zero and one are not prime numbers.

And this is what I need to do:

Design a circuit for this device using:
-An appropriately sized decoder
-An appropriately sized MUX where N1 is used to drive the inputs
to the MUX. Draw the MUX as a block diagram.

How exactly would I go about doing this? I'm not even sure where to start, tbh.

What do you mean "where N1 is used to drive the inputs"?

Are you being asked to design a single circuit using exactly one decoder and one MUX and nothing else?

 

What do you mean "where N1 is used to drive the inputs"?

The variable N1 is...being used to drive the inputs, in the block diagram? I'm not exactly sure how to describe it, but in the examples done in class, there would always be 3 variables attached to the bottom of the block diagram, and a 4th variable on the left, connected to the inputs. The one on the left connected to the inputs is the "variable used to drive the inputs".

Are you being asked to design a single circuit using exactly one decoder and one MUX and nothing else?

Pretty much, yeah.

First thing to do would be to create a truth table to determine what the output of the device should be for every possible combination of inputs to the device.

| Inputs | Output decimal | N3N2N1N0 | Y
0|0000| 0
1|0001| 0
2|0010| 1
3|0011| 1
4|0100| 0
5|0101| 1
6|0110| 0
7|0111| 1
8|1000| 0
9|1001| 0
10|1010| 0
11|1011| 1
12|1100| 0
13|1101| 1
14|1110| 0
15|1111| 0

Okay, now what?

 

-An appropriately sized MUX where N1 is used to drive the inputs
to the MUX. Draw the MUX as a block diagram.

Are you allowed to use additional, basic logic gates?

 

Are you allowed to use additional, basic logic gates?

Yeah, pretty sure we are. Like, if the input-driving variable was complimented for one of the inputs, the professor would draw a line towards the input, then an inverter/NOT gate, then continue the line to the input.

 

The variable N1 is...being used to drive the inputs, in the block diagram? I'm not exactly sure how to describe it, but in the examples done in class, there would always be 3 variables attached to the bottom of the block diagram, and a 4th variable on the left, connected to the inputs. The one on the left connected to the inputs is the "variable used to drive the inputs".

Is this indicative of your understanding of a MUX? That there are some variables attached to the bottom and a variable attached on the left? If so, then you are in for a long, frustrating road. You need to get a much better handle on the basics.

It sounds like you are being given a pretty convoluted set of specs. But maybe it will work out smoothly in the end.

| Inputs | Output decimal | N3N2N1N0 | Y
0|0000| 0
1|0001| 0
2|0010| 1
3|0011| 1
4|0100| 0
5|0101| 1
6|0110| 0
7|0111| 1
8|1000| 0
9|1001| 0
10|1010| 0
11|1011| 1
12|1100| 0
13|1101| 1
14|1110| 0
15|1111| 0

Okay, now what?

Since you are being required to use only N1 as your MUX input, that means that each channel can either be HI, LO, or N1 (and never N1').

So reorganize your table so that you have N3N2N0 as your primary inputs and N1 as a secondary input. Try something like

N3N2N0|N1=0|N1=1
000||
001||
010||
011||
100||
101||
110||
111||

Most things look like they work out nicely, but the last row will give problems.

 

Yeah, that's more similar to what the professor used for MUX problems.

Here's one example that was done in class:

http://i.imgur.com/H17qvO6.png (Except the F(X,Y,Z) on the end of the block diagram should be an F(W,X,Y,Z) )

The variable "Y" is what I was talking about when I said "variable to drive the inputs" and "1 variable on the left".

Perhaps I'm just getting a bit confused with the wording of this specific problem? The result of the table you two are giving me to solve is looking similar to the F(W,X,Y,Z) = (1,2,3 ...) etc, and I know how to solve and create a block diagram, from there.

 

But notice in your example that an inverter was used. I think you need an inverter at one of the inputs here, but you have said that you can't use an inverter.

 

But notice in your example that an inverter was used. I think you need an inverter at one of the inputs here, but you have said that you can't use an inverter.

Uh..no, I said we CAN use inverters. The "NOT" there was because in another computer logic class, the professor called the inverter a "NOT gate", and I'm not really sure which term is more commonly known.

But anyways, given that I can find the minterms of the function here, I can go about it just as I did in that example I linked. Is that the way I'm supposed to do it? Because that example, I understand perfectly.

 

Uh..no, I said we CAN use inverters. The "NOT" there was because in another computer logic class, the professor called the inverter a "NOT gate", and I'm not really sure which term is more commonly known.

But anyways, given that I can find the minterms of the function here, I can go about it just as I did in that example I linked. Is that the way I'm supposed to do it? Because that example, I understand perfectly.

I didn't see the prior post before making my last one. So, yeah, all you need is a an inverter and an 8:1 MUX.

I don't know what the decoder is supposed to be for. I was starting to think you were supposed to use the decoder to make an inverter.

 

Yeah, I'm not entirely sure what the Decoder is used for. The handout labeled "3 x 8 Decoder" shows a block diagram with inputs (X,Y,Z) and outputs of minterms 0-8, using inverters and AND gates.

Is that what I'm supposed to draw out? a 4 x 16 decoder block diagram? (seeing as there's 4 variables)

 

I don't know what the point would be. You can implement ANY function of four variables with one inverter (NOT gate) and one 8:1 MUX. No decoder needed.

Similarly, you can implement any function of four variables with a 1:16 decoder and a 16-input (worst case) OR gate.

I don't know if they are trying to say that you can implement this design using a small decoder and a small MUX (and perhaps no inverter). It's not obvious to me, but then again there are a number of possibilities that would have to be explored.

 

I don't know what the point would be. You can implement ANY function of four variables with one inverter (NOT gate) and one 8:1 MUX. No decoder needed.

Yeah, I'm not sure what the point would be, either. I'll have to ask the professor tomorrow what exactly he means by "use a decoder".

 

Do that. And be sure to let us know what he says. We might learn something or, at least, we might get a tad bit of insight into what profs are asking these days.

 

Asked the prof, and he said that yes, all I have to do is draw out a decoder block diagram for that part of the problem. I took out the handout he gave us showing a 3x8 decoder and asked "So I just draw the same as this, but 4x16?" and he said yeah.

 

Weird. So you are supposed to draw the internal circuit for a part that you don't then use? How does he then claim that "appropriately sized" means a 4x6? I would argue that, for this problem, a 1x2 is "appropriately sized" since it would allow you to use the decoder in place of the inverter and, hence, use exactly the two components specified in the problem.