I have designed an H-bridge circuit using IR4110 Mosfets. Q1 and Q4 are OFF, Q2 and Q3 are conducting. Gate of Q1 is left floating. Q2 being high side, its gate is connected to Vcc + 12v. Gate of Q3 is connected to PWM signal (12v square wave 15kHz, 70% duty cycle) for motor speed control through a 10 ohm resistor. Gate of Q4 is grounded through 10ohm resistor. All MOSFETs have 10k resistor between their gate and source, though it is not shown in the diagram.
Now, when gate of Q3 is high, it conducts, but at the same time Q1 also conducts for a brief moment, causing shoot-through and heating up Q1. When I hooked up the gate pin and source pin of Q1 to a DSO, it is observed that Vgs of Q1 goes above its Vgs threshold for a brief moment, turning it ON, which is undesired. The exact reason is unclear.
This never happens for IR4115 MOSFETs, which I am currently using without any such problems. Maybe it is because Vgs threshold of 4115 is higher than that of 4110.
Any explanation or suggestions for design modification will be highly appreciated

 

Gate of Q1 is left floating

If you leave the gate of a MOSFET floating then it may conduct or it may be off or it might fluctuate between on and off. The gate has a very resistance so any leakage or pickup from nearby signals can switch the MOSFET if you want it to be off connect the gate to 0V.

 

If you leave the gate of a MOSFET floating then it may conduct or it may be off or it might fluctuate between on and off. The gate has a very resistance so any leakage or pickup from nearby signals can switch the MOSFET if you want it to be off connect the gate to 0V.

Hi thanks for the reply, all mosfets have 10k resistor between gate and source (not indicated in the diagram though), so that Vgs is 0v in the absence of signal. It is not a good idea to directly ground high side gates, as Vgs might go well below its maximum negative limit

 

Does your gate drive generate dead band timing, thats what is normally used
to insure no overlap occurs.

Notice PH1 and PH2 do not overlap, in this configurator for PWM one sets the number of
clocks both phases of PWM are off.



Regards, Dana.

 

In my design the the top MOSFET Q1 is simply kept OFF when the lower MOSFET Q3 is driven by PWM. So there is no overlapping or deadtime issue

 

the 4110 is a huge gate C, and that is reflected in turn off
delay and other timing. And timing is speced with Rg =
2.6 ohms. So your 10 ohms will aggravate the switching speed
issues.

Very challenging design, and the 4115 may be working as it
has substantially lower C....which tells us design margin may
be inadequate ....


Regards, Dana.

 

Vgs of Q1 goes above its Vgs threshold for a brief moment, turning it ON, which is undesired. The exact reason is unclear.

I'd guess Cgs and Cds play a part. As the load is inductive, flyback current through the FET body diode will cause heating of Q1.

 

Cgd is indeed the culprit.

Upon lowside MOSFET switching on you get a steep rise in upper ones Vds. This steps through Cgd and rises Vgs as you noticed on the scope.

The point is that 10 kohm pull down is far from enough to keep Vgs=0 dynamically, you need a much lower value.
You can try to even directly short G and S if nothing else makes this impractical.

Different MOSFETs may have different Cgd, threshold voltage, Cgs (the latter helps shunting disturbing current) and may seem to be working ok.

This is however only partially true, as you just learned, those are marginally working circuits, they depend from little controllable parameters.
Reliable design calls for taking care of these details.