This is my first time posting on this forum.
I would like to implement a circuit that allows a digital circuit powered by 3V3 to switch 3V3A to 3.3V or 0V.
The gate voltage of the MOSFET is connected to the output of a simple flip-flop.

However, when the gate voltage was applied high (3.3V) after implementing the circuit attached below, the voltage of 3V3A was about 2.4V, not 0V.

For those of you who are much more advanced than me, I would like to know why I get these results.

 

What load do you have on the 3V3A? The SBSS84L P-MOSFET on resistance is in the 4 to 10 ohm range and that's
with 5V on the gate, not 3.3V.

https://www.onsemi.com/pdf/datasheet/bss84lt1-d.pdf

 

The PMOS gate must be pulled low for a PMOS mosfet to turn on.
The PMOS gate must be pulled high for a PMOS mosfet to turn off.

 

What load do you have on the 3V3A? The SBSS84L P-MOSFET on resistance is in the 4 to 10 ohm range and that's
with 5V on the gate, not 3.3V.

https://www.onsemi.com/pdf/datasheet/bss84lt1-d.pdf

I think the load is pretty normal.
The load is the MAX31865 and surrounding circuitry, a voltage divider for measuring the onboard thermistor, one Neopixel, and one small SH1106-based OLED.

Rather, I didn't know that there were separate MOSFETs for 3.3V and 5V. If what you said is true, could you recommend a SOT-23 MOSFET for 3.3V with similar specifications?
Since I have little circuit design experience, it would be really helpful if you could help me.

It's currently 4 am where I live, and I can't immediately get replacement parts, but I'll update the test results after experimenting with replacements.

 

The PMOS gate must be pulled low for a PMOS mosfet to turn on.
The PMOS gate must be pulled high for a PMOS mosfet to turn off.

Thank you so much!
I'll try to attach pull-up and pull-down on the gate tomorrow.

 

Thank you so much!
I'll try to attach pull-up and pull-down on the gate tomorrow.

You don't need R26.
Connect the gate to Q, then connect a 100k pull-up resistor from mosfet gate to source. When Q is high, PMOS will be off.

If you want the PMOS on when Q is high, use a different DFF that has complimentary outputs, and connect the gate to Qbar.
Or, use an NMOS to invert the Q output.

 

I solved the problem.
I made a separate circuit of the initial design and tested it, and it worked completely normally.
There was a problem with the load, and the problem was solved by eliminating the problematic part where 3V3 was leaking into 3V3A.

Your advice didn't directly help me, but thank you for your effort.