Hey there!

Im designing a simple CMOS amplifier at the moment in Virtuoso - a simple NMOS common source with a diode connected PMOS load.

When i lower my bias point for a larger small-signal gain, I'm experiencing a dramatic drop in bandwidth. Would anyone have any reason why this might be?

Cheers

 

Hey there!

Im designing a simple CMOS amplifier at the moment in Virtuoso - a simple NMOS common source with a diode connected PMOS load.

When i lower my bias point for a larger small-signal gain, I'm experiencing a dramatic drop in bandwidth. Would anyone have any reason why this might be?

Cheers

Typically gain*bandwidth is a rough constant. If you increase the gain you decrease the bandwidth. Also consider your miller capacitance, gets effectively larger for higher gain.

 

Please upload the schematic as 800x600 gif or jpg file, some png file may causing a file size big than its should be.