My task is to design Moore sequence detector. As my teacher said, my graph is okay.


I wrote down next states and outputs, then decided which flip-flops I'll use. With Karnaugh tables, I miminalized functions for them. My problem is, it's not working correctly. When I'm simulating it in Xilinx, after my desired sequence "01010" on the input, I don't get logical 1 on the output. My question is: are my K-tables and way of thinking correct? Below my scheme in Xilinx and the outcome:




Also, my VHDL code:

clock <= '1', '0' after 20 ns, '1' after 40 ns, '0' after 60 ns, '1' after 80 ns, '0' after 100 ns, '1' after 120 ns, '0' after 140 ns, '1' after 160 ns, '0' after 180 ns, '1' after 200 ns,'0' after 220 ns, '1' after 240 ns, '0' after 260 ns, '1' after 280 ns, '0' after 300 ns, '1' after 320 ns, '0' after 340 ns, '1' after 360 ns, '0' after 380 ns, '1' after 400 ns, '0' after 420 ns, '1' after 440 ns, '0' after 460 ns, '1' after 480 ns, '0' after 500 ns, '1' after 520 ns, '0' after 540 ns, '1' after 560 ns, '0' after 580 ns, '1' after 600 ns;
xinput <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns, '0' after 400 ns, '1' after 500 ns;

 

You state diagram should accept an initial 01010, but it is not correct. For instance, shouldn't it accept 0101010 since it ends with the desired sequence. Will your state diagram accept that?

To troubleshoot your system, include the internal state with the simulation output so that you can see if it is walking through the state diagram like you expect.

One recommendation to make your like easier -- label your states starting with S0. This allows you to immediately map the state label to the state encoding. For instance, S5 encodes as 101.

BTW, Thank you so much for posting your work!

 

Next time I'll label states as you said, good idea and it will simplify whole process a bit.
By saying "internal state" you meant to connect output to every ff output like this?


and the outcome:

So it detects "01010101" combination. I forgot to mention, it should be without reset (not sure how it's called in english, I mean it can continue as long as sequence matches).

 

You made some kind of change to the circuit since the youtput result is no longer the same that it was.

It is detecting 01010, it is NOT detecting 0101010 -- look at youput after that much of the sequence is read. Your machine is resetting to the initial state after recognizing a valid input sequence, so it starts over and asserts HI again after reading the sequence all over again (i.e., [01010]1[01010]). But is SHOULD assert for each of the following:

[01010]
01[01010]
0101[01010]
010101[01010]
01010101[01010]

Keep in mind that the assertion happens while the input symbol following the match is read -- that's a consequence of it being a Moore machine.

 

I changed my VHDL code. I was playing with it again and managed to make it work - I shouldn't change data on a positive edge. My final outcome looks like this, maybe someone will find it useful (I know clock is not entirely correct, but it's a matter of few seconds):


To change it to accept sequences you've wrote, I would have to change my state diagram, but it's not that hard to correct now.
Thanks for the help!