Do you think it would be possible to produce a PWM output with the CD74HC195E shift register, if you took the PWM signal split it into two and inverted one of them, then placed one output to the Clock and the other to the Master Reset?
The register would be in Parallel mode.
The PWM would be anything from 3khz to 5khz.
I'm concerned about a timing problem with changing the reset line and the clock at the same time.
The PWM signal will be generated by a PSoC micro so I can place many buffers in series on the clock line to delay it...will that work?
Also if anybody knows of a more appropriate chip please let me know, all I really need is a set of gated buffers with the inputs on one side of the chip, and the outputs on the other side and have complementary outputs.
And, yes I know about the CD4081, but that chip does not meet one very important requirement. (see above about the input and output configuration) Which is also a shame because I have 25 in stock.
So this is basically what I need...

The register would be in Parallel mode.
The PWM would be anything from 3khz to 5khz.
I'm concerned about a timing problem with changing the reset line and the clock at the same time.
The PWM signal will be generated by a PSoC micro so I can place many buffers in series on the clock line to delay it...will that work?
Also if anybody knows of a more appropriate chip please let me know, all I really need is a set of gated buffers with the inputs on one side of the chip, and the outputs on the other side and have complementary outputs.
And, yes I know about the CD4081, but that chip does not meet one very important requirement. (see above about the input and output configuration) Which is also a shame because I have 25 in stock.
So this is basically what I need...
