# Microprocessor Multi SPI connection

#### ilginsarican

Joined Jul 13, 2017
99
Hello,
I use MK60DN512VLL10.
I have to use at least 65 ADC data, probably I will use ADS1158 16-Channel, 16-Bit Analog-to-Digital Converter.
I want to know that How many SPIs can hardware connect to the processor's SPI port?

#### jpanhalt

Joined Jan 18, 2008
9,079
Hello,
I use MK60DN512VLL10.
I have to use at least 65 ADC data, probably I will use ADS1158 16-Channel, 16-Bit Analog-to-Digital Converter.
I want to know that How many SPIs can hardware connect to the processor's SPI port?
How many pins do you have available for $$\overline{SS}$$?

#### ilginsarican

Joined Jul 13, 2017
99
How many pins do you have available for $$\overline{SS}$$?
Sorry What is
$\overline{SS}$
?

#### ilginsarican

Joined Jul 13, 2017
99
Is it like chip select?

#### bertus

Joined Apr 5, 2008
20,451
Hello,

You can select the ADC's using the CS\ line.
@jpanhalt just asked how many lines you have available for the select lines.
Eventualy you could use a demultiplexer.

Bertus

#### jpanhalt

Joined Jan 18, 2008
9,079
With the MCU as master and the target device as slave, the $$\overline{ss}$$ idles high. To send to the target, make SS for it low. It's like an address.

Yes, it is chip select. Microchip tends to use SS for SPI with PIC's. Sorry. I originally wrote CS, but edited it.

#### ilginsarican

Joined Jul 13, 2017
99
With the MCU as master and the target device as slave, the $$\overline{ss}$$ idles high. To send to the target, make SS for it low. It's like an address.

Yes, it is chip select. Microchip tends to use SS for SPI with PIC's. Sorry. I originally wrote CS, but edited it.
It's ok.
MK60DN512VLL10 has three SPI modules,so there are three CS pin, but I want to connect six slave to a SPI module of master(MK60DN512VLL10).Is it possible?
I've read this "In digital electronics, the fan-out of a logic gate output is the number of gate inputs it can drive".

#### jpanhalt

Joined Jan 18, 2008
9,079
It is my understanding that those CS pins identified with each module (e.g., CS1, CS2,CS3) can be used to address the MCU when it is slave or can be used by the MCU to address slaves. In addition, one can use any output pin of the MCU when it is master to control the CS pin of a slave. So, to address 6 slaves independently would require 6 pins on the MCU, unless multiplexing is used as @bertus suggested.

Since SPI is always duplex, any 6 or more pins not otherwise used, including but not limited to CS1..CS3 can be used to send and receive data from 6 or more slaves (ignoring multiplexing). Since you have so many ADC's to consider, you may need multiplexing at some level.

#### ilginsarican

Joined Jul 13, 2017
99
It is my understanding that those CS pins identified with each module (e.g., CS1, CS2,CS3) can be used to address the MCU when it is slave or can be used by the MCU to address slaves. In addition, one can use any output pin of the MCU when it is master to control the CS pin of a slave. So, to address 6 slaves independently would require 6 pins on the MCU, unless multiplexing is used as @bertus suggested.

Since SPI is always duplex, any 6 or more pins not otherwise used, including but not limited to CS1..CS3 can be used to send and receive data from 6 or more slaves (ignoring multiplexing).
I've found this picture, I think I can use any IO pin as CS,it is ok.
But how many slave can connect to CLK or SDO or SDI?
I guess there must be a limit for MCU pins.
How can I determine the maximum slave can be connected?(Because of fan-out)

#### nsaspook

Joined Aug 27, 2009
7,181
The input load from each SPI slave input pin will likely be less than 50uA and the MISO will tri-state with CS is high so current limited DC fanout is unlikely to be a problem. What you might want a buffer for is to drive the line impedance to reduce reflections and ringing while driving the reactive load of PCB traces and input pins with a large number of devices. Serial resistors (30-50 ohm typical) should be included near the driving pins for SPI signals to improve signal integrity at high clock speeds or long wires.

#### Picbuster

Joined Dec 2, 2013
996
It's ok.
MK60DN512VLL10 has three SPI modules,so there are three CS pin, but I want to connect six slave to a SPI module of master(MK60DN512VLL10).Is it possible?
I've read this "In digital electronics, the fan-out of a logic gate output is the number of gate inputs it can drive".
When mpu is master you do not need the cs or ss pin from mpu.
You can set all SDO, SDI and clock parallel makes sure that each SDO and SDI has a serial resistor.
next thing is to use a demux 4 in 16 out each output goes to the adc CS (chip select)

simple works for me with 7 devices ( RTC, 4 x mcp3551, vincu-2(ftdi) and gsm)

#### MrChips

Joined Oct 2, 2009
20,882
I believe that there is no definitive answer to your question. You will have to examine the specifications of the ADC and MCU.

There are two considerations: static fan-out and dynamic fan-out.

For static fan-out, you need to look at the current and voltage drive capability of the output gate and compare that with the current and switching threshold voltages of all inputs. A typical fan-out of TTL gates is 10. Typical fan-out of 4000 series CMOS gates is 50.

Dynamic fan-out is even more complicated. In this case, you need to consider the total input capacitance of all the inputs and the rise and fall times of the switching signal. The limiting factor will be the clock frequency of the SPI CLK. You will have to reduce the clock frequency in order to meet the switching requirements.

65 slave devices seem very high. You may investigate using signal buffers.

#### ilginsarican

Joined Jul 13, 2017
99
I believe that there is no definitive answer to your question. You will have to examine the specifications of the ADC and MCU.

There are two considerations: static fan-out and dynamic fan-out.

For static fan-out, you need to look at the current and voltage drive capability of the output gate and compare that with the current and switching threshold voltages of all inputs. A typical fan-out of TTL gates is 10. Typical fan-out of 4000 series CMOS gates is 50.

Dynamic fan-out is even more complicated. In this case, you need to consider the total input capacitance of all the inputs and the rise and fall times of the switching signal. The limiting factor will be the clock frequency of the SPI CLK. You will have to reduce the clock frequency in order to meet the switching requirements.

65 slave devices seem very high. You may investigate using signal buffers.
Actually I have 65 ADC Datas,I will use 16-Channel, 16-Bit Analog-to-Digital Converter IC which communicates SPI

#### MrChips

Joined Oct 2, 2009
20,882
Actually I have 65 ADC Datas,I will use 16-Channel, 16-Bit Analog-to-Digital Converter IC which communicates SPI
I do not understand what you mean by 65 ADC data.

#### ilginsarican

Joined Jul 13, 2017
99
I do not understand what you mean by 65 ADC data.

I mean I've 65 sensors.I will read signals from each.
1 sensor means 1 ADC data

#### MrChips

Joined Oct 2, 2009
20,882
I mean I've 65 sensors.I will read signals from each.
1 sensor means 1 ADC data

Fan-in and fan-out with five ADCs should not be a problem.

#### nsaspook

Joined Aug 27, 2009
7,181
I do not understand what you mean by 65 ADC data.

I would guess he needs to monitor 65 analog signals, each ADC has a 16 input multiplexer so 65/16 (remainder rounded up to a whole device ) = number of devices.

#### ilginsarican

Joined Jul 13, 2017
99

Fan-in and fan-out with five ADCs should not be a problem.
Do you know how can I verify with calculation?
Shoul I use digital input current value of MCU and digital output current of Analog-to-Digital Converter IC?

#### MrChips

Joined Oct 2, 2009
20,882
Five SPI slave units is not a problem.

For /SS, you can either use five GPIO pins from the MCU or three GPIO pins into a 3-to-8 line decoder.

#### John P

Joined Oct 14, 2008
1,808
Or connect a shift register, 74HC595 or equivalent, to the SPI Clk and Data lines and clock a single low bit into it, then use just one extra port pin to strobe the data to the shift register outputs. Those outputs would be the /SS lines for the ADC's; there could be 8 of them.